[Windows ARM64] Complete v0.26 native runtime and Rust frontend

[khmyznikov]

Purpose

Complete the native Windows ARM64 runtime on top of the existing v026_win_arm64
port by applying the non-overlapping runtime pieces validated in
SystemPanic/vllm-windows#82.

The baseline already contains the v0.26 ports of the reproducible build script,
SM103/SM120 FA2 and Marlin support, DeepGEMM, FlashMLA, ARM64 CUDA paths, spin
waits, the CUDA-header alignment overlay, and UMA safetensors synchronization.
This PR deliberately keeps those implementations and adds only the missing
pieces:

• Port the Rust frontend to Windows: TCP listeners, Windows process groups,
  recursive termination, Ctrl-Break handling, and Unix-only IPC guards.
• Package and discover vllm-rs.exe, Rust .pyd extensions, and other
  precompiled Windows .pyd artifacts correctly.
• Recognize SM12x for FA4 only when the CUTLASS DSL runtime is importable;
  otherwise fail closed to the supported fallback.
• Pin triton-lang/triton-windows at
  4790f15d480bc32d0c8c2c58dfb68a3dd53eb826, including its Gluon support.
• Make full wheel builds require the native Rust frontend by default, with an
  explicit -SkipRustFrontend escape hatch.
• Support both conventional uv (Scripts) and conda-style (Library\bin)
  ARM64 environments in the PowerShell build entry point.

The originally proposed CUTLASS indirect-launch layer and Windows ARM64 source
exclusions were dropped after review. A clean rebuild confirmed that the
baseline CUDA-header overlay is sufficient for the unchanged direct-launch
SM120 FP8/NVFP4 sources.

The branch is five focused commits on top of 6629ecfb2 (v026_win_arm64).
Generated documentation and build artifacts are excluded.

No existing open PR covers this combination of missing Rust frontend, packaging,
FA4 gating, and build-environment support on the v0.26 Windows ARM64 baseline.

Test Plan

Validated on Windows 11 ARM64 with NVIDIA RTX Spark N1X (SM12.1), CUDA 13.4,
CPython 3.13 ARM64, MSVC 14.51, Rust 1.95, full Perl, and native protoc.

cargo check --workspace --locked
cargo fmt --all -- --check

python -m pytest --confcutdir=tests/vllm_flash_attn `
  tests/vllm_flash_attn/test_flash_attn_interface.py -q

ruff check `
  vllm/vllm_flash_attn/flash_attn_interface.py `
  tests/vllm_flash_attn/test_flash_attn_interface.py

python -c "from triton.experimental import gluon; from triton.experimental.gluon import language as gl"

.\tools\build-win-arm64.ps1 `
  -VenvDir C:\Dev\vllm-windows\.venv `
  -CudaPath "C:\Program Files\NVIDIA GPU Computing Toolkit\CUDA\v13.4" `
  -MaxJobs 2 `
  -SkipBuild

cmake --build .\build\win-arm64-config `
  --target _C_stable_libtorch `
  --parallel 2

.\tools\build-win-arm64.ps1 `
  -VenvDir C:\Dev\vllm-windows\.venv `
  -CudaPath "C:\Program Files\NVIDIA GPU Computing Toolkit\CUDA\v13.4" `
  -PerlPath C:\Dev\perl-host\Library\bin\perl.exe `
  -ProtocPath C:\Dev\vllm-windows\.venv\Library\bin\protoc.exe `
  -WheelDir .\dist\win-arm64-sm120-sm103-marlin-fa2-rust `
  -MaxJobs 2

The wheel was extracted and every .pyd/.exe inspected with
dumpbin /headers. FA2 was inspected with cuobjdump --list-elf. All packaged
native modules were imported from the extracted artifact, followed by an
end-to-end Qwen3.8 NVFP4 generation smoke test. The post-review CUTLASS rebuild
was additionally exercised with focused FP8 and NVFP4 numerical comparisons
against PyTorch references.

Test Result

• Native Rust workspace check and rustfmt passed.
• FA4 runtime/capability tests: 6 passed; Ruff passed.
• Direct Gluon imports pass with the reviewer-referenced Windows ARM64 Triton
  artifact.
• Configure-only validation fetched
  triton-lang/triton-windows@4790f15d480bc32d0c8c2c58dfb68a3dd53eb826 and
  generated successfully.
• With the indirect-launch change removed, _C_stable_libtorch compiled the
  unchanged dense and blockwise SM120 FP8/NVFP4 sources using the baseline
  CUDA-header overlay.
• Native cutlass_scaled_mm FP8 and cutlass_scaled_fp4_mm NVFP4 numerical
  checks passed against PyTorch references on SM12.1.
• The initial integration build completed all 238 targets and built
  vllm-0.26.0+cu134-cp313-cp313-win_arm64.whl (357,105,782 bytes).
• The Rust release build packaged vllm-rs.exe and _rust_tool_parser.pyd.
• All 12 packaged .pyd/.exe binaries report AA64 machine (ARM64).
• FA2 contains 76 native sm_120.cubin and 76 native sm_100.cubin entries.
• Exact-wheel imports passed for core, MoE, QUTLASS, FlashMLA, Rust parser,
  allocator, filesystem I/O, spinloop, DeepGEMM, and FA2 modules.
• Qwen3.8 NVFP4 loaded using native CUTLASS FP8/NVFP4, vendored DeepGEMM,
  Triton/FLA GDN, and Triton attention, then generated 8 coherent tokens:
  The sky appears blue due to a.

No model-quality evaluation was run because these changes port
platform/build/runtime behavior without changing model weights or numerical
algorithms. The numerical kernel checks and end-to-end generation smoke test
guard the affected execution paths.

AI assistance was used. The contributor reviewed every changed line and
validation result.

---

Essential Elements of an Effective PR Description Checklist

• Purpose and relationship to the baseline PR are documented.
• Test commands are provided.
• Configure, build, binary, import, Rust, unit-test, numerical-kernel, and
  model results are provided.
• Documentation requirements were considered; generated documentation is
  intentionally excluded.

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[vortex-captain]

Thanks for putting this PR together!

I wanted to double-check commit 28af25b1. The CUtensorMap alignment issue had already been handled on v026_win_arm64 with a generated cuda.h overlay. It uses 64-byte alignment under MSVC while retaining 128-byte alignment for other compilers. With that overlay, a clean v0.26 Windows ARM64 build compiled the affected SM120 sources successfully.

We also ran unsloth/Qwen3.8-27B-NVFP4 with Doopeworld/Qwen3.8-27B-DSpark-vLLM as the DSpark draft and --linear-backend cutlass. vLLM selected CutlassNvFp4LinearKernel and CutlassFP8ScaledMMLinearKernel; target and draft warmup and CUDA graph capture completed, the server became healthy, and generation requests completed successfully.

Could you please help confirm what you observed for these two modified kernels on the environment where the original issue appeared: did they fail during compilation, or did compilation succeed and the problem instead appear at runtime as wrong numerical results, a crash or hang, or poor performance? It would also be helpful to know whether they work there with the current v026_win_arm64 branch but without commit 28af25b1's indirect-launch changes. I may be missing a compiler or runtime configuration where the overlay alone is insufficient, and your confirmation would help clarify.

[khmyznikov]

Thanks for flagging this. You were right that 28af25b1 is unnecessary on the current v026_win_arm64 baseline.

I went back through the original build history. The workaround was introduced during the compile-porting phase for by-value CUTLASS GemmKernel::Params; I could not find a separately reproduced runtime wrong-result, crash, hang, or performance failure attributable to these two kernels. The baseline CUDA-header overlay was already present before that commit.

I removed the indirect-launch changes and Windows ARM64 source exclusions, then rebuilt _C_stable_libtorch cleanly with the baseline overlay. The unchanged direct-launch build compiled and linked all relevant sources, including:

• scaled_mm_c3x_sm120.cu
• scaled_mm_sm120_fp8.cu
• scaled_mm_blockwise_sm120_fp8.cu
• nvfp4_scaled_mm_sm120_kernels.cu
• nvfp4_blockwise_moe_kernel.cu

The resulting ARM64 extension (SHA256 95F55B6ADC99FAEF1F0032FBC66DDD79613E85388BF026F27BB4AF12B7C0F433) passed:

• native FP8 cutlass_scaled_mm: max error 0.12480545043945312
• native NVFP4 cutlass_scaled_fp4_mm: max error 0.12497711181640625, with CutlassNvFp4LinearKernel selected
• end-to-end Qwen3.8 NVFP4 generation: CutlassFP8ScaledMMLinearKernel and CutlassNvFp4LinearKernel selected, 8 tokens generated successfully (The sky appears blue due to a)

I therefore rewrote the branch to drop 28af25b1 entirely rather than retaining an original/revert pair. The PR now has no CUTLASS kernel or source-exclusion diff.