A RISC-V Single Cycle Processor which is done in verilog.
-
Updated
Jul 20, 2020 - Verilog
A RISC-V Single Cycle Processor which is done in verilog.
A custom SoC soft microcontroller implemented on an Artix-7 Basy3 Board designed to read and process data from an external circuit to accurately determine what is scanned and how much of it is scanned
Collaborative project using Vivado to design a CPU capable of executing R, I, and J instructions with scalable architecture.
Add a description, image, and links to the risc-architecture-processor topic page so that developers can more easily learn about it.
To associate your repository with the risc-architecture-processor topic, visit your repo's landing page and select "manage topics."