Rollup of 14 pull requests

Cargo.lock

@@ -4055,19 +4055,29 @@ dependencies = [
  "rustc_lexer",
  "rustc_lint_defs",
  "rustc_macros",
- "rustc_middle",
  "rustc_parse",
  "rustc_proc_macro",
  "rustc_serialize",
  "rustc_session",
  "rustc_span",
  "rustc_structures",
- "scoped-tls",
  "smallvec",
  "thin-vec",
  "tracing",
 ]
 
+[[package]]
+name = "rustc_expand_queries"
+version = "0.0.0"
+dependencies = [
+ "rustc_ast",
+ "rustc_expand",
+ "rustc_middle",
+ "rustc_proc_macro",
+ "rustc_span",
+ "scoped-tls",
+]
+
 [[package]]
 name = "rustc_feature"
 version = "0.0.0"
@@ -4271,6 +4281,7 @@ dependencies = [
  "rustc_data_structures",
  "rustc_errors",
  "rustc_expand",
+ "rustc_expand_queries",
  "rustc_feature",
  "rustc_fs_util",
  "rustc_hir",

compiler/rustc_codegen_cranelift/src/inline_asm.rs

@@ -443,11 +443,12 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
                 .supported_types(self.arch, true)
                 .iter()
                 .map(|(ty, _)| ty.size())
+                .filter_map(InlineAsmSize::fixed_size_bytes)
                 .max()
-                .unwrap();
-            let align = rustc_abi::Align::from_bytes(reg_size.bytes()).unwrap();
+                .expect("expected fixed-size type");
+            let align = rustc_abi::Align::from_bytes(reg_size).unwrap();
             let offset = slot_size.align_to(align);
-            *slot_size = offset + reg_size;
+            *slot_size = offset + rustc_abi::Size::from_bytes(reg_size);
             offset
         };
         let mut new_slot = |x| new_slot_fn(&mut slot_size, x);

compiler/rustc_codegen_gcc/src/asm.rs

@@ -692,7 +692,9 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r",
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w",
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
-        InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
+        InlineAsmRegClass::AArch64(
+            AArch64InlineAsmRegClass::preg | AArch64InlineAsmRegClass::ffr,
+        ) => {
             unreachable!("clobber-only")
         }
         InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "Sg",
@@ -807,7 +809,9 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
         | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
             cx.type_vector(cx.type_i64(), 2)
         }
-        InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
+        InlineAsmRegClass::AArch64(
+            AArch64InlineAsmRegClass::preg | AArch64InlineAsmRegClass::ffr,
+        ) => {
             unreachable!("clobber-only")
         }
         InlineAsmRegClass::Amdgpu(_) => cx.type_i32(),
@@ -1056,7 +1060,9 @@ fn modifier_to_gcc(
         | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
             if modifier == Some('v') { None } else { modifier }
         }
-        InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
+        InlineAsmRegClass::AArch64(
+            AArch64InlineAsmRegClass::preg | AArch64InlineAsmRegClass::ffr,
+        ) => {
             unreachable!("clobber-only")
         }
         InlineAsmRegClass::Amdgpu(_) => None,

compiler/rustc_codegen_llvm/src/asm.rs

@@ -732,18 +732,25 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
                     format!("{{{}{}}}", class, idx)
                 }
             } else if let Some(idx) = a64_vreg_index(reg) {
-                let class = if let Some(layout) = layout {
-                    match layout.size.bytes() {
+                let class = match layout {
+                    Some(layout)
+                        if matches!(
+                            layout.backend_repr,
+                            BackendRepr::SimdScalableVector { .. }
+                        ) =>
+                    {
+                        'z'
+                    }
+                    Some(layout) => match layout.size.bytes() {
                         16 => 'q',
                         8 => 'd',
                         4 => 's',
                         2 => 'h',
                         1 => 'd', // We fixup i8 to i8x8
                         _ => unreachable!(),
-                    }
-                } else {
+                    },
                     // We use i64x2 as the type for discarded outputs
-                    'q'
+                    None => 'q',
                 };
                 format!("{{{}{}}}", class, idx)
             } else if let Some(idx) = hexagon_reg_pair_index(reg) {
@@ -775,7 +782,10 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
             AArch64(AArch64InlineAsmRegClass::reg) => "r",
             AArch64(AArch64InlineAsmRegClass::vreg) => "w",
             AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
-            AArch64(AArch64InlineAsmRegClass::preg) => unreachable!("clobber-only"),
+            // Although the above link suggests its just 'Upa', llvm's own tests seem to suggest its
+            // '@3Upa'. (see "src/llvm-project/clang/test/CodeGen/AArch64/sve-inline-asm-datatypes.c" line 139)
+            AArch64(AArch64InlineAsmRegClass::preg) => "@3Upa",
+            AArch64(AArch64InlineAsmRegClass::ffr) => unreachable!("clobber-only"),
             Arm(ArmInlineAsmRegClass::reg) => "r",
             Arm(ArmInlineAsmRegClass::sreg)
             | Arm(ArmInlineAsmRegClass::dreg_low16)
@@ -885,7 +895,7 @@ fn modifier_to_llvm(
                 modifier
             }
         }
-        AArch64(AArch64InlineAsmRegClass::preg) => unreachable!("clobber-only"),
+        AArch64(AArch64InlineAsmRegClass::preg | AArch64InlineAsmRegClass::ffr) => None,
         Arm(ArmInlineAsmRegClass::reg) => None,
         Arm(ArmInlineAsmRegClass::sreg) | Arm(ArmInlineAsmRegClass::sreg_low16) => None,
         Arm(ArmInlineAsmRegClass::dreg)
@@ -990,7 +1000,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
         AArch64(AArch64InlineAsmRegClass::vreg) | AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
             cx.type_vector(cx.type_i64(), 2)
         }
-        AArch64(AArch64InlineAsmRegClass::preg) => unreachable!("clobber-only"),
+        AArch64(AArch64InlineAsmRegClass::preg) => cx.type_scalable_vector(cx.type_i1(), 16),
+        AArch64(AArch64InlineAsmRegClass::ffr) => unreachable!("clobber-only"),
         Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
         Arm(ArmInlineAsmRegClass::sreg) | Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
         Arm(ArmInlineAsmRegClass::dreg)

compiler/rustc_codegen_ssa/src/back/link.rs

@@ -4129,7 +4129,7 @@ fn add_lld_args(
     // `lld` as the linker.
     //
     // Note that wasm targets skip this step since the only option there anyway
-    // is to use LLD but the `wasm32-wasip2` target relies on a wrapper around
+    // is to use LLD but component-producing targets rely on a wrapper around
     // this, `wasm-component-ld`, which is overridden if this option is passed.
     if !sess.target.is_like_wasm {
         cmd.cc_arg("-fuse-ld=lld");

compiler/rustc_codegen_ssa/src/mir/retag.rs

@@ -73,7 +73,7 @@ impl<'a, 'tcx, V> RetagPlan<V> {
             //  the outermost `Box` is what determines the permission that gets created.
             ty::Adt(adt, _) if adt.is_box() => Self::visit_box(bx, layout, is_fn_entry),
             // Skip traversing for everything inside of `MaybeDangling`
-            ty::Adt(adt, _) if adt.is_maybe_dangling() => None,
+            _ if layout.ty.is_like_maybe_dangling() => None,
             _ => Self::walk_value(bx, layout, is_fn_entry),
         }
     }

compiler/rustc_const_eval/src/interpret/validity.rs

@@ -7,7 +7,6 @@
 use std::borrow::Cow;
 use std::fmt::{self, Write};
 use std::hash::Hash;
-use std::mem;
 use std::num::NonZero;
 
 use either::{Left, Right};
@@ -1528,15 +1527,10 @@ impl<'rt, 'tcx, M: Machine<'tcx>> ValueVisitor<'tcx, M> for ValidityVisitor<'rt,
                     BackendRepr::Memory { .. } => unreachable!()
                 }
             }
-            ty::Adt(adt, _) if adt.is_maybe_dangling() => {
-                let old_may_dangle = mem::replace(&mut self.may_dangle, true);
-
-                let inner = self.ecx.project_field(val, FieldIdx::ZERO)?;
-                self.visit_value(&inner)?;
-
-                self.may_dangle = old_may_dangle;
-            }
             _ => {
+                let old_may_dangle = self.may_dangle;
+                self.may_dangle |= val.layout.ty.is_like_maybe_dangling();
+
                 // default handler
                 try_validation!(
                     self.walk_value(val),
@@ -1546,6 +1540,8 @@ impl<'rt, 'tcx, M: Machine<'tcx>> ValueVisitor<'tcx, M> for ValidityVisitor<'rt,
                     Ub(InvalidVTableTrait { vtable_dyn_type, expected_dyn_type }) =>
                         InvalidMetaWrongTrait { expected_dyn_type, vtable_dyn_type },
                 );
+
+                self.may_dangle = old_may_dangle;
             }
         }
 

compiler/rustc_expand/Cargo.toml

@@ -20,7 +20,6 @@ rustc_hir = { path = "../rustc_hir" }
 rustc_lexer = { path = "../rustc_lexer" }
 rustc_lint_defs = { path = "../rustc_lint_defs" }
 rustc_macros = { path = "../rustc_macros" }
-rustc_middle = { path = "../rustc_middle" }
 rustc_parse = { path = "../rustc_parse" }
 # We must use the proc_macro version that we will compile proc-macros against,
 # not the one from our own sysroot.
@@ -29,7 +28,6 @@ rustc_serialize = { path = "../rustc_serialize" }
 rustc_session = { path = "../rustc_session" }
 rustc_span = { path = "../rustc_span" }
 rustc_structures = { path = "../rustc_structures" }
-scoped-tls = "1.0"
 smallvec = { version = "1.8.1", features = ["union", "may_dangle"] }
 thin-vec = "0.2.19"
 tracing = "0.1"

compiler/rustc_expand/src/lib.rs

@@ -23,7 +23,3 @@ pub mod config;
 pub mod expand;
 pub mod module;
 pub mod proc_macro;
-
-pub fn provide(providers: &mut rustc_middle::query::Providers) {
-    providers.derive_macro_expansion = proc_macro::provide_derive_macro_expansion;
-}

compiler/rustc_expand/src/mbe/diagnostics.rs

@@ -6,7 +6,6 @@ use rustc_attr_ir::diagnostic::{CustomDiagnostic, Directive, FormatArgs};
 use rustc_data_structures::fx::FxHashSet;
 use rustc_errors::{Applicability, Diag, DiagCtxtHandle, DiagMessage, pluralize};
 use rustc_macros::Subdiagnostic;
-use rustc_middle::bug;
 use rustc_parse::parser::{Parser, Recovery, token_descr};
 use rustc_session::parse::ParseSess;
 use rustc_span::source_map::SourceMap;
@@ -203,7 +202,7 @@ impl BestFailure {
 impl<'dcx, 'matcher> Tracker<'matcher> for CollectTrackerAndEmitter<'dcx, 'matcher> {
     fn prepare(&mut self, which_matcher: WhichMatcher, matcher: &'matcher [MatcherLoc]) {
         if self.current.is_some() {
-            bug!("`Self::after_arm()` was not called to clean up context");
+            panic!("`Self::after_arm()` was not called to clean up context");
         }
 
         self.current = Some((which_matcher, matcher));
@@ -236,12 +235,12 @@ impl<'dcx, 'matcher> Tracker<'matcher> for CollectTrackerAndEmitter<'dcx, 'match
             }
             Failure => {
                 if self.best_failure.is_none() {
-                    bug!("A matching failure occurred but `Self::failure()` was not called");
+                    panic!("A matching failure occurred but `Self::failure()` was not called");
                 }
             }
             Ambiguity => {
                 if self.result.is_none() {
-                    bug!("An ambiguity error occurred but `Self::ambiguity()` was not called");
+                    panic!("An ambiguity error occurred but `Self::ambiguity()` was not called");
                 }
             }
             ErrorReported(guar) => self.result = Some((self.root_span, guar)),
@@ -253,7 +252,7 @@ impl<'dcx, 'matcher> Tracker<'matcher> for CollectTrackerAndEmitter<'dcx, 'match
 
     fn failure(&mut self, parser: &Parser<'_>) {
         let Some((which_matcher, _)) = self.current else {
-            bug!("`Self::prepare()` was not called to initialize context");
+            panic!("`Self::prepare()` was not called to initialize context");
         };
 
         let mut token = parser.token;
@@ -290,7 +289,7 @@ impl<'dcx, 'matcher> Tracker<'matcher> for CollectTrackerAndEmitter<'dcx, 'match
 
     fn ambiguity(&mut self, parser: &Parser<'_>) {
         let Some((_, matcher)) = self.current else {
-            bug!("`Self::prepare()` was not called to initialize context");
+            panic!("`Self::prepare()` was not called to initialize context");
         };
 
         #[expect(

compiler/rustc_expand/src/mbe/macro_parser.rs

@@ -80,7 +80,6 @@ pub(crate) use ParseResult::*;
 use rustc_ast::token::{self, DocComment, NonterminalKind, Token, TokenKind};
 use rustc_data_structures::fx::FxHashMap;
 use rustc_errors::{Diag, ErrorGuaranteed};
-use rustc_middle::span_bug;
 use rustc_parse::parser::{ParseNtResult, Parser, token_descr};
 use rustc_span::{Ident, MacroRulesNormalizedIdent, Span};
 
@@ -732,17 +731,14 @@ impl TtParser {
         // `NamedParseResult`. Otherwise, it's an error.
         let mut ret_val = FxHashMap::default();
         for loc in matcher {
-            if let &MatcherLoc::MetaVarDecl { span, bind, .. } = loc
+            if let &MatcherLoc::MetaVarDecl { bind, .. } = loc
                 && ret_val
                     .insert(MacroRulesNormalizedIdent::new(bind), res.next().unwrap())
                     .is_some()
             {
                 // Duplicate binds are checked for when the macro definition is processed,
                 // and should have prevented the definition from ever being used.
-                span_bug!(
-                    span,
-                    "duplicate meta-variable binding went undetected at macro definition"
-                )
+                panic!("duplicate meta-variable binding went undetected at macro definition")
             }
         }
         ret_val