Skip to content

[Entropic R32-P5, taped out 5-stage RV32I CPU] - SHORT RESOURCE TITLE HERE #102

Description

@Entropify

Resource Title

Entropic R32-P5, taped out 5-stage RV32I CPU

Resource Description

Hello!

I would like to share a recent project I completed. It is a 5 stage pipelined rv32i cpu featuring dynamic branch prediction. It was written, verified, performance tested, and taped out complete from scratch and all by me.

I know that there are already existing similar RISC-V cores in this repo. My reason for wanting to add is this that I am a recent high school graduate who is stepping foot into university this September. Thus I completely self-taught the knowledge and tools to build this. I tried to my best to document all of my design choices, architectural structure, issues faced, general plan I took to make the project, and all external resources used in my readme. I hope that my project could offer a fresh perspective specifically for those who are less experienced in RISC-V and VLSI in general, but still want to start learning and build cool projects.

Thank you for reading and considering!

Resource Link

https://github.com/Entropify/Entropic_R32-P5_RISC-V

Required Background (Optional)

No response

Additional Details (Optional)

No response

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Labels

documentationImprovements or additions to documentation

Type

No type

Projects

No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions