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LZhaoM
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Feb 6, 2026
LZhaoM
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…ock settings from devicetree data The mmc driver has the same phase values for all meson platforms. However, some platforms (and even some boards) require different values. This patch transfers the values from the set in the code to the variables in the device-tree file. Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
…, tx, rx phase clock settings. Use phase 270 for core MMC clock on axg meson boards. Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
…tion amlogic,mmc-phase - amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values: 0: CLK_PHASE_0 - 0 phase 1: CLK_PHASE_90 - 90 phase 2: CLK_PHASE_180 - 180 phase 3: CLK_PHASE_270 - 270 phase By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value. Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in> - rpardini: in 6.4, Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt is gone and now replaced by Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
On the Radxa Zero with Samsung eMMC, I/O errors possibly occur when
accessing the eMMC:
```
[ 8454.110446] I/O error, dev mmcblk1, sector 64 op 0x1:(WRITE) flags 0x8800 phys_seg 62 prio class 2
```
Reproduce the issue by running the following command for a few hours:
```
while uptime; do echo -n "rock" | \
sudo /usr/sbin/cryptsetup luksFormat \
--type luks2 \
--batch-mode /dev/mmcblk1;\
done
```
Configuring the MMC clock phase to 270 phase can solve the issue. Tested
by running the above command for 7 hours and didn't see any I/O error.
This patch is based on:
https://github.com/armbian/build/blob/a50ac096bd551d91ae21dd78d5ab51859db057ee/patch/kernel/archive/meson64-6.18/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch
Co-authored-by: Jiali Chen <chenjiali@radxa.com>
Signed-off-by: Zhaoming Luo <luozhaoming@radxa.com>
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