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[arch] ADR-001 also needs DDR3L clarification on top of bandwidth amendment (Stays #28)
stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#33 In popsolutions/MAST;[arch] Amend ADR-001 — DDR3 bandwidth claim 12.8 GB/s is theoretical, real is 1.5-2.4 GB/s on ECP5+open toolchain
stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#32 In popsolutions/MAST;[cross-stream] interconnect block port surface must match InnerJib7EA intercard_link stub
cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination neededstream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#29 In popsolutions/MAST;[arch] Decide whether contr_rd_data should also be wire (asymmetry with core1_rd_data)
stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#28 In popsolutions/MAST;[hw] Re-verify single-deep contr_rd_pending latch when gpu_controller.sv migrates
stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#21 In popsolutions/MAST;[hw] Delete src/global_mem_controller.sv when gpu_die.sv migrates to direct AXI4 adapter (PR-2b)
stream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#20 In popsolutions/MAST;[cross-stream] inter-card link bandwidth + latency model for scheduler
cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination neededstream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primarystream-3Software Stack (Agent 3) — driver, runtime, GGML, SpankerSoftware Stack (Agent 3) — driver, runtime, GGML, SpankerStatus: Open.#18 In popsolutions/MAST;[cross-stream] expose queryable axi4_mem_model state for ggml-spanker integration tests
cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination neededstream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primarystream-3Software Stack (Agent 3) — driver, runtime, GGML, SpankerSoftware Stack (Agent 3) — driver, runtime, GGML, SpankerStatus: Open.#17 In popsolutions/MAST;[cross-stream] LitePCIe has no ECP5 PHY — rev-A host-link path is unsupported upstream
cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination neededhuman-attentionStrategic / financial / governance — needs humanStrategic / financial / governance — needs humanstream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primarystream-2FPGA Hardware (Agent 2) — KiCad, Stays primaryFPGA Hardware (Agent 2) — KiCad, Stays primarystream-4Open FPGA Upstream (Agent 4) — yosys, prjtrellis, LiteDRAM patchesOpen FPGA Upstream (Agent 4) — yosys, prjtrellis, LiteDRAM patchesStatus: Open.#13 In popsolutions/MAST;[meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff
metaSprint coordination, planningSprint coordination, planningStatus: Open.#11 In popsolutions/MAST;[arch] ADR-014 — Inter-card link architecture choice (multi-card parallelism)
cross-streamTouches multiple streams — coordination neededTouches multiple streams — coordination neededstream-1RTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryRTL Architect (Agent 1) — SystemVerilog, cocotb, MAST primaryStatus: Open.#9 In popsolutions/MAST;