v0.4.2

v0.4.2

Highlights

• csim (AHDL-to-C Transpiler): Native C code simulation acceleration, enabled by default
• Compiler API: Public compile() function with parameter binding and type specification
• CHStone Benchmarks: Added 10 module class implementations (AES, ADPCM, Motion, MIPS, SHA, Blowfish, DFADD, DFMUL, DFDIV, GSM)
• Internal refactoring: IR immutability, old IR removal, Scope class restructuring, type hints

v0.4.1

v0.4.1

Highlights

• Python simulation debug: watch() for signal tracing with VCD and text log output
• Module constructor arguments: Support function and tuple arguments in module constructors
• Build system migration: Migrated to pyproject.toml with uv and ruff, GitHub Actions CI

Bug Fixes

• Fix TypeSpecializer infinite loop
• Fix constopt array inlining and class constants
• Fix aliasvar field symbol crash
• Fix AHDLVarReducer field variable protection
• Fix WaitTransformer trailing codes with META_WAIT
• Auto-reg variables crossing clksleep in timed scopes
• Remove stale ctor FSM state signal from generated Verilog

v0.4.0

Features

• timed scheduling
• New python based simulator

v0.3.6

• Fix maximum recursion issue
• Add an assertion for lack of resources
• Add support for printing source text
• Fix simplification of branch predicate
• Add support for parametrized module

v0.3.5

• Add support for package import
• Improve scope selection rules

v0.3.4

Supports loop flattening.

v0.3.3

• Support loop pipelining & unrolling

v0.3.2

main features of version 0.3.2

• Support for nested module
• Support for register array
• Improved optimization

v0.3.1

main features of version 0.3.1

• @pure decorator for pure Python code execution (experimental feature)

v0.3.0

main features of version 0.3.0

• Introducing of module-based design
• Introducing of built-in libraries
  • polyphony.io
  • polyphony.typing
  • polyphony.timing
• Improved optimization