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rdl: make sure mem codegen accounts for entry byte width#471

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Aaron-Hartwig merged 3 commits intomainfrom
aaron/mem-range-fix
Feb 27, 2026
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rdl: make sure mem codegen accounts for entry byte width#471
Aaron-Hartwig merged 3 commits intomainfrom
aaron/mem-range-fix

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@Aaron-Hartwig
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fixes #470

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Testing this now.

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This appears to be working.

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The first bug covered up a second one (fixed by 8547e19): we were trimming the address before doing the bytes-to-entry conversion (divide by 4), leading us to lose the upper two bits in the event we were attempting to address anything in the 1024-4095 range. Prior to this we were just wrapping around in the 0-1023 space.

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lgtm, one note about how I think the addr construction can be simplified with 1 fewer resize.

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Simulation is blocked by an nvc regression: nickg/nvc#1438.

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Simulation is blocked by an nvc regression: nickg/nvc#1438.

I rolled back our CI environment from nvc-1.19.1 to nvc-1.18.2 as this seems to have broken in nvc-1.19.0.

ubuntu@fpga-ci:~$ nvc --version
nvc 1.18.2 (Using LLVM 18.1.3)

@Aaron-Hartwig Aaron-Hartwig merged commit d2b888c into main Feb 27, 2026
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@Aaron-Hartwig Aaron-Hartwig deleted the aaron/mem-range-fix branch February 27, 2026 16:18
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post code buffer only holds 1024 codes, not 4096

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