Derive the SPI divider base from the active GPSPI clock source

[ainyan03]

FreqToClockDiv() receives a base clock from getApbFrequency(), which reports a fixed 80 MHz on every target. That was true while the SPI peripheral was fed from APB, but the newer chips select a clock source and, on some of them, run it through pre-dividers first. Nothing configures that source unless the ESP-IDF driver acquires the bus, and Arduino builds take the Arduino bus mutex instead, so the source is left at whatever reset or the Arduino HAL happened to leave.

The dividers were therefore computed against a base clock that is not the real one, and the resulting SCLK could be either far below or well above the requested value.

Measured on hardware

Requested vs. actual SCLK before these changes:

Target	Path	Requested	Actual
ESP32-S3	Arduino	40 MHz	80 MHz
ESP32-S3	Arduino, CPU scaled to 40 MHz	40 MHz	80 MHz
ESP32-C61	ESP-IDF without bus lock	40 MHz	80 MHz
ESP32-P4	Arduino	80 MHz	40 MHz
ESP32-C5	Arduino	40 MHz	24 MHz
ESP32-H2	Arduino	40 MHz	16 MHz

The overspeeding cases are the reason for the first two commits: a panel asked for 40 MHz and got twice that.

ESP32, ESP32-S2 and ESP32-C6 are unaffected and measured unchanged.

What the commits do

Clamp SPI clock dividers to their register widths — FreqToClockDiv() could produce a CLKDIV_PRE wider than its field, spilling into neighbouring bits; with a low enough request the spill reached SPI_CLK_EQU_SYSCLK and drove the bus at full speed when a slow clock was asked for. The limits now come from the register definitions, so each target keeps its own field width.

Use the active GPSPI source clock for divider calculations — the base clock is derived from the clock-source selector and pre-dividers that are actually programmed, instead of assuming 80 MHz. Bus acquisition moves ahead of the calculation because acquiring can change the source, and reading first would use a stale base for the first transaction. The crystal frequency is read at runtime rather than assumed, which matters on parts that ship with something other than 40 MHz.

Select faster GPSPI sources for Arduino transactions — where a better source exists, it is selected for the duration of a transaction and the saved fields are restored when it ends, so other users of the bus see the state they left. The takeover only runs while the bus lock is held, only when it produces a strictly closer write clock without overspeeding either requested rate, and is undone when the bus is released or destroyed.

Verification

• Hardware: ESP32, ESP32-S3, ESP32-C6, ESP32-H2, ESP32-C5, ESP32-C61 and ESP32-P4, all measured with this branch. For every target the SCLK computed from the clock registers and the SCLK derived from transfer timing agree, and both match the requested rate within the limits of integer division.
• ESP32-C3 and ESP32-C2 were reviewed but not measured. ESP32-C3 shares its decoding path with ESP32-S3.

One user-visible effect: an ESP32-C5 board whose panel is configured for 40 MHz was running at 24 MHz, and a full-screen fill went from 52.5 ms to 32.1 ms.