[dv] Enable DRAM backdoor for the UVM TB

doc/ref/dev_guide.md

@@ -43,8 +43,6 @@ cmake -B build/sw -S sw
 cmake --build build/sw -j $(nproc)
 ```
 
-Outputs with the suffix "_sram" exist only for UVM-based tests, as they presently lack a DRAM backdoor-load mechanism.
-
 The boot-ROM output with the "_scrambled" suffix is the only binary run through the ROM image scrambling script.
 Attempting to run any unscrambled binary from the scrambled ROM will be blocked by the in-hardware ROM checker.
 

hw/top_chip/dv/common/sim_dram_axi/sim_dram_axi.core

@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors (COSMIC project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:mocha_dv:sim_dram_axi:0.1"
+description: "DRAM simulation wrapper providing an AXI-accessible mock memory for chip-level simulation."
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:prim:ram_1p
+      - lowrisc:mocha:top_chip_system
+    files:
+      - sim_dram_wrapper.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_dv

hw/top_chip/dv/verilator/dram_wrapper_sim.sv → hw/top_chip/dv/common/sim_dram_axi/sim_dram_wrapper.sv

@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module dram_wrapper_sim (
+module sim_dram_wrapper (
   // Clock and reset
   input  logic clk_i,
   input  logic rst_ni,

hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv

@@ -29,20 +29,20 @@ class top_chip_dv_base_vseq extends uvm_sequence;
   // In the extended test vseq, add this function call to the start of body().
   extern function void sw_symbol_backdoor_access(input string symbol,
                                                  inout bit [7:0] data[],
-                                                 input chip_mem_e mem = ChipMemSRAM,
+                                                 input chip_mem_e mem = ChipMemDRAM,
                                                  input bit does_not_exist_ok = 0,
                                                  input bit is_write = 0);
   // Backdoor-read a const symbol in SW to make decisions based on SW constants.
   // Wrapper function for reads via sw_symbol_backdoor_access.
   extern function void sw_symbol_backdoor_read(input string symbol,
                                                inout bit [7:0] data[],
-                                               input chip_mem_e mem = ChipMemSRAM,
+                                               input chip_mem_e mem = ChipMemDRAM,
                                                input bit does_not_exist_ok = 0);
   // Backdoor-override a const symbol in SW to modify the behavior of the test.
   // Wrapper function for writes via sw_symbol_backdoor_access.
   extern function void sw_symbol_backdoor_overwrite(input string symbol,
                                                     input bit [7:0] data[],
-                                                    input chip_mem_e mem = ChipMemSRAM,
+                                                    input chip_mem_e mem = ChipMemDRAM,
                                                     input bit does_not_exist_ok = 0);
   // General-use function to backdoor write a byte of data to any selected memory type
   extern function void mem_bkdr_write8(input chip_mem_e mem,
@@ -118,7 +118,7 @@ endtask : wait_for_sw_test_done
 function void top_chip_dv_base_vseq::sw_symbol_backdoor_access(
   input string symbol,
   inout bit [7:0] data[],
-  input chip_mem_e mem = ChipMemSRAM,
+  input chip_mem_e mem = ChipMemDRAM,
   input bit does_not_exist_ok = 0,
   input bit is_write = 0);
 
@@ -179,7 +179,7 @@ endfunction : sw_symbol_backdoor_access
 
 function void top_chip_dv_base_vseq::sw_symbol_backdoor_read(input string symbol,
                                               inout bit [7:0] data[],
-                                              input chip_mem_e mem = ChipMemSRAM,
+                                              input chip_mem_e mem = ChipMemDRAM,
                                               input bit does_not_exist_ok = 0);
 
   sw_symbol_backdoor_access(symbol, data, mem, does_not_exist_ok, 0);
@@ -188,7 +188,7 @@ endfunction : sw_symbol_backdoor_read
 
 function void top_chip_dv_base_vseq::sw_symbol_backdoor_overwrite(input string symbol,
                                                    input bit [7:0] data[],
-                                                   input chip_mem_e mem = ChipMemSRAM,
+                                                   input chip_mem_e mem = ChipMemDRAM,
                                                    input bit does_not_exist_ok = 0);
 
   sw_symbol_backdoor_access(symbol, data, mem, does_not_exist_ok, 1);
@@ -198,7 +198,7 @@ function void top_chip_dv_base_vseq::mem_bkdr_write8(input chip_mem_e mem,
                                       input bit [bus_params_pkg::BUS_AW-1:0] addr,
                                       input byte data);
   byte prev_data;
-  if (mem == ChipMemSRAM) begin
+  if (mem inside {ChipMemSRAM, ChipMemDRAM}) begin
     prev_data = p_sequencer.mem_bkdr_util_h[mem].read8(addr);
     p_sequencer.mem_bkdr_util_h[mem].write8(addr, data);
   end else begin
@@ -210,7 +210,7 @@ endfunction : mem_bkdr_write8
 function void top_chip_dv_base_vseq::mem_bkdr_read8(input chip_mem_e mem,
                                      input bit [bus_params_pkg::BUS_AW-1:0] addr,
                                      output byte data);
-  if (mem == ChipMemSRAM) begin
+  if (mem inside {ChipMemSRAM, ChipMemDRAM}) begin
     data = p_sequencer.mem_bkdr_util_h[mem].read8(addr);
   end else begin
     `dv_fatal($sformatf("Backdoor %0s access not yet supported", mem.name()))

hw/top_chip/dv/env/top_chip_dv_env.sv

@@ -52,7 +52,7 @@ function void top_chip_dv_env::build_phase(uvm_phase phase);
 
   // Initialize the sw logger interface.
   foreach (cfg.mem_image_files[i]) begin
-    if (i inside {ChipMemSRAM}) begin
+    if (i inside {ChipMemSRAM, ChipMemDRAM}) begin
       cfg.sw_logger_vif.add_sw_log_db(cfg.mem_image_files[i]);
     end
   end

hw/top_chip/dv/env/top_chip_dv_env_pkg.sv

@@ -17,8 +17,9 @@ package top_chip_dv_env_pkg;
   `include "dv_macros.svh"
 
   typedef enum {
+    ChipMemROM,
     ChipMemSRAM,
-    ChipMemROM
+    ChipMemDRAM
   } chip_mem_e;
 
   typedef chip_mem_e chip_mem_list_t[$];

hw/top_chip/dv/tb/chip_hier_macros.svh

@@ -8,6 +8,7 @@
 `define SRAM_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_ram.mem
 `define TAG_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_tag_ram.mem
 `define ROM_MEM_HIER `SYSTEM_HIER.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.mem
+`define DRAM_MEM_HIER tb.u_dram_wrapper.u_ext_mem.mem
 
 // Testbench related
 `define SIM_SRAM_IF u_sim_sram.u_sim_sram_if

hw/top_chip/dv/tb/tb.sv

@@ -66,7 +66,7 @@ module tb;
   top_pkg::axi_dev_req_t  sw_dv_req;
   top_pkg::axi_dev_resp_t sw_dv_resp;
 
-  dram_wrapper_sim u_dram_wrapper (
+  sim_dram_wrapper u_dram_wrapper (
     // Clock and reset.
     .clk_i      (dut.clkmgr_clocks.clk_main_infra),
     .rst_ni     (dut.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]),
@@ -189,21 +189,37 @@ module tb;
         .system_base_addr     (top_pkg::SRAMBase                  )
       );
 
-      // Zero-initialising the SRAM ensures valid BSS.
+      // Zero-initialise SRAM to prevent X-propagation through its AXI path.
       m_mem_bkdr_util[ChipMemSRAM].clear_mem();
       `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemSRAM], `SRAM_MEM_HIER)
 
       m_mem_bkdr_util[ChipMemROM] = new(
         .name                 ("mem_bkdr_util[ChipMemROM]"        ),
-        .path                 (`DV_STRINGIFY(`ROM_MEM_HIER)        ),
-        .depth                ($size(`ROM_MEM_HIER)                ),
-        .n_bits               ($bits(`ROM_MEM_HIER)                ),
+        .path                 (`DV_STRINGIFY(`ROM_MEM_HIER)       ),
+        .depth                ($size(`ROM_MEM_HIER)               ),
+        .n_bits               ($bits(`ROM_MEM_HIER)               ),
         .err_detection_scheme (mem_bkdr_util_pkg::ErrDetectionNone),
-        .system_base_addr     (top_pkg::RomCtrlMemBase             )
+        .system_base_addr     (top_pkg::RomCtrlMemBase            )
       );
 
       `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemROM], `ROM_MEM_HIER)
 
+      // Zero-init DRAM with a direct SV loop (not clear_mem) before loading the vmem: prim_ram_1p
+      // starts as X, and reads outside the binary range propagate into tag-controller FIFOs (DataKnown_A).
+      for (int unsigned dram_init_i = 0; dram_init_i < $size(`DRAM_MEM_HIER); dram_init_i++) begin
+        `DRAM_MEM_HIER[dram_init_i] = '0;
+      end
+
+      m_mem_bkdr_util[ChipMemDRAM] = new(
+        .name                 ("mem_bkdr_util[ChipMemDRAM]"       ),
+        .path                 (`DV_STRINGIFY(`DRAM_MEM_HIER)      ),
+        .depth                ($size(`DRAM_MEM_HIER)              ),
+        .n_bits               (longint'($size(`DRAM_MEM_HIER))*$bits(`DRAM_MEM_HIER[0])),
+        .err_detection_scheme (mem_bkdr_util_pkg::ErrDetectionNone),
+        .system_base_addr     (top_pkg::DRAMBase                  )
+      );
+
+      `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemDRAM], `DRAM_MEM_HIER)
 
       // TODO MVy, see if required
       // Zero-initialise the SRAM Capability tags, otherwise TL-UL FIFO assertions will fire;

hw/top_chip/dv/top_chip_sim.core

@@ -13,6 +13,7 @@ filesets:
   files_dv:
     depend:
       - lowrisc:mocha_dv:sim_sram_axi:0.1
+      - lowrisc:mocha_dv:sim_dram_axi:0.1
       - lowrisc:dv:sw_test_status
       - lowrisc:dv:sw_logger_if
       - lowrisc:mocha_dv:top_chip_dv_test
@@ -29,7 +30,6 @@ filesets:
     files:
       - tb/tb.sv
       - tb/chip_hier_macros.svh: {is_include_file: true}
-      - verilator/dram_wrapper_sim.sv
     file_type: systemVerilogSource