rtl: integrate packetized LSC-1 on ULX3S by Th0rgal · Pull Request #24 · lfglabs-dev/lean-silicon

Th0rgal · 2026-07-26T12:45:18Z

What changed

connects the packet frontend to the existing 8-bit ready/valid MinCore datapath through an explicit stream adapter
makes lean_silicon_lsc1 the packetized product top while preserving a separate raw MinCore diagnostic top
expands packet reception to 256 bytes and implements NEGOTIATE, STATUS, SET/XOR/MUL, DEREF Cell/Pc/Fp, JUMP, staged RETIRE, transaction guards and atomic state updates
adds lsc1_field_encoder, reusing the streaming multiplier to verify encoded JUMP destinations
adds packet-safe UART BREAK abort/recovery and fixes false 0xff reception after framing errors
extends the host compiler/runtime and RTL↔Python differential tests through DEREF and JUMP
adds the physical packet UART driver, official-program runner, adversarial transport tests and reproducible ULX3S package recipe
incorporates the latest PR fpga: ULX3S v3.1.8 smoke + 1 Mbaud UART bridge to exact lean_silicon_lsc1 (MinCore) #16 foundation head c2ea7f1b299d5e293eaa1524335e671d78dc4999

Root causes fixed

The initial adapter deadlocked SET/XOR because those MinCore operations emit output during payload ingestion. The UART receiver also re-armed while BREAK was still low, producing a spurious 0xff and BAD_SOF. Finally, the 94-byte packet buffer could not hold the 103-byte JUMP request. These paths now have regression coverage.

Validation at head `33b4c81416d367e230b4ecb28b1c857d43f4bbab`

266 executable-model tests pass
231 FPGA harness tests pass (one expected pyserial environment skip)
MinCore, legacy UART, packet UART, adversarial frontend, mutation and byte-exact RTL/Python differential simulations pass
DEREF Cell/Pc/Fp and JUMP taken/not-taken success vectors pass in RTL differential tests
BAD_POINTER, DEREF_MISMATCH, BAD_BRANCH_PROPOSAL and BAD_INVERSE recovery vectors pass
Yosys hierarchy/check and generic synthesis pass
latest completed route: 44.02 MHz PASS at 25 MHz; 18,262 LUT4 and 5,940 FF

Physical ULX3S evidence

SRAM-only validation was performed on LFE5U-85 IDCODE 0x41113043 at 1 Mbaud; no flash write was performed.

bitstream SHA-256: af78dcea8ac2a493b50f1a7fc293c20ed81f4052bdb58c6443c58e46da76d723
two builds produced byte-identical bit/config/SVF outputs
official assert_set_xor_mul completes all 13 records, including JUMP, reaches PC 15 and reports full MATCH
final 12 memory cells compare byte-for-byte with the frozen Rust artefact
physical DEREF Cell/Pc/Fp, BAD_POINTER and BAD_INVERSE pass
partial JUMP + UART BREAK emits no response or partial commit; STATUS reports the abort and a following SET/RETIRE succeeds

This physical image was produced before the final merge-only reconciliation commit. The interrupted exact-33b4c81 rebuild must be rerun on the new hardware host before claiming an authenticated exact-head package.

Current limits / handoff

external host-side BLAKE3 service is not integrated yet; RTL honestly advertises only the implemented interpreter feature
Lean/RTL refinement and additional framing/reset/backpressure formal properties remain incomplete
PR fpga: ULX3S v3.1.8 smoke + 1 Mbaud UART bridge to exact lean_silicon_lsc1 (MinCore) #16 is still the base of this stacked draft; reconcile the stack only after the PR fpga: ULX3S v3.1.8 smoke + 1 Mbaud UART bridge to exact lean_silicon_lsc1 (MinCore) #16 writer publishes its new clean-toolchain head
regenerate an exact-head package on the DGX Spark, compare artefacts, then perform one authenticated physical campaign from that exact image

Note

High Risk
Large RTL and protocol-surface change to the product top, transaction semantics, and host runtime; correctness relies on simulation/differential evidence rather than full formal refinement.

Overview
lean_silicon_lsc1 is now the packetized product top: it instantiates lsc1_packet_frontend instead of raw leanvm_b_stream_alu, with the old stream-ALU harness moved to lean_silicon_lsc1_mincore for diagnostics.

New RTL glue (lsc1_stream_adapter, lsc1_field_encoder) drives MinCore over the existing 8-bit stream and re-encodes pointer witnesses for DEREF/JUMP. The packet frontend grows to the full scalar subset—NEGOTIATE, STATUS, SET/XOR/MUL, DEREF Cell/Pc/Fp, JUMP, staged RETIRE—via the stream adapter instead of a dedicated GF128 multiplier block; RX payload storage widens to 256 bytes for JUMP frames.

Host and validation extend through DEREF/JUMP (frozen fixture now full MATCH), plus RTL↔Python byte-exact differential tests, packet UART sims, and a physical lsc1_packet_uart driver. FPGA adds packet-mode UART (BREAK abort, no 0x7f in-band abort), ulx3s_packet_top / build recipe, and CI Yosys closure over the packet RTL stack.

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Th0rgal and others added 13 commits July 26, 2026 13:37

rtl: integrate packetized LSC-1 FPGA path

1a9deaa

test: preserve historical FPGA provenance

cd7096e

build: archive packet FPGA routing outputs

5198876

ci: run RTL differential in SystemVerilog job

4891b7b

fix: isolate canonical packet host imports

18fa84a

host: execute DEREF and JUMP programs

e0b2d89

rtl: execute DEREF and JUMP packets

be423c4

ci: include field encoder in source closure

ec70e5a

build: refresh source checksums

e33c73c

merge: reconcile latest ULX3S foundation

33b4c81

Fix LSC1 packet inverse and XOR backsolve paths

a650ba5

Fix differential test checksum

03a47bc

Merge base branch into packet integration

a119ce2

Th0rgal marked this pull request as ready for review July 26, 2026 20:32

Merge latest base branch updates

ab32bf2

chatgpt-codex-connector Bot reviewed Jul 26, 2026

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Comment thread fpga_harness/host/lsc1_packet_uart.py Outdated

Comment thread fpga_harness/host/lsc1_packet_uart.py Outdated

Bound packet UART exchanges by deadline

4c7f4a3

chatgpt-codex-connector Bot reviewed Jul 26, 2026

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Comment thread fpga_harness/host/lsc1_packet_uart.py Outdated

Validate physical scalar results before retire

1f9d185

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Comment thread fpga_harness/host/lsc1_packet_uart.py

Validate retirement acknowledgement

df8ca93

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Comment thread fpga_harness/host/lsc1_packet_uart.py Outdated

Comment thread fpga_harness/host/lsc1_packet_uart.py

Require fresh bounded packet startup

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Comment thread fpga_harness/host/lsc1_packet_uart.py

Comment thread fpga_harness/host/lsc1_packet_uart.py Outdated

Tighten physical program completion checks

dcd6bf3

Th0rgal merged commit 79c7ff4 into fpga/ulx3s-smoke-uart-mincore Jul 27, 2026
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Th0rgal mentioned this pull request Jul 27, 2026

Integrate qualified PR #24 packetized LSC-1 onto main #26

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What changed

Root causes fixed

Validation at head 33b4c81416d367e230b4ecb28b1c857d43f4bbab

Physical ULX3S evidence

Current limits / handoff

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Th0rgal commented Jul 26, 2026 •

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Validation at head `33b4c81416d367e230b4ecb28b1c857d43f4bbab`