fpga: ULX3S v3.1.8 smoke + 1 Mbaud UART bridge to exact lean_silicon_lsc1 (MinCore)

.github/workflows/ci.yml

@@ -12,6 +12,9 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683
+        with:
+          # Provenance validates a documented ancestor, not just the checkout.
+          fetch-depth: 0
       - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065
         with:
           python-version: "3.13"

.gitignore

@@ -19,3 +19,18 @@ formal/stream_alu_mul_pulse_induction/
 formal/stream_alu_mul_pulse_cover/
 openlane/
 reports/
+
+# Scratch outputs of the ULX3S build scripts. The scripts archive the copies
+# that matter under results/.
+fpga/ulx3s/smoke_top.*
+fpga/ulx3s/ulx3s_top.*
+!fpga/ulx3s/smoke_top.sv
+!fpga/ulx3s/ulx3s_top.sv
+
+# Archived build evidence. The blanket *.log rule above would otherwise drop
+# the synthesis and route logs that make an immutable bitstream reviewable.
+!results/**/*.log
+
+# ecppack is silent on success; an empty log is not evidence.
+results/**/ecppack*.log
+results/.ulx3s-smoke-uart.publish.lock

SHA256SUMS

@@ -1,5 +1,5 @@
-152ebd1753fdc29f26b782a4062080a67449149438fd5026c166a25029d7d47b  ./.github/workflows/ci.yml
-c5a00dfb7ec29979b10d186838f02a1efe2b42126cda0c65df658d6b4c7bc543  ./.gitignore
+520f032c9983bb98548e3316724b8218ef92730c6e3309309fdf6835597e4559  ./.github/workflows/ci.yml
+e01c466509630117b96ee5ddac3ad887ec95a932cfd5b1efcff77fe4f3891133  ./.gitignore
 cfc7749b96f63bd31c3c42b5c471bf756814053e847c10f3eb003417bc523d30  ./LICENSE
 ca1b6b510bfeb5dc906aa0862e95d962c2901c246fa10fa72296d1666239d601  ./MANIFEST.md
 c4e56018f86fd8b6fd1cd2e2cb39370b0501e8f83a1d7aeceab163457f9d60e4  ./Makefile
@@ -34,8 +34,9 @@ b81b89574ed84c67b64ae7b56001bf9d03b9d66be2bed7977d8adc715481eafb  ./docs/PROTOCO
 0d787acfaa683bf07cedea98ba403d51079593b50f84b48ee199a479cc35b099  ./docs/SEMANTICS.md
 6ec7c4c80628391da706725be1a2361ae8eb2ee014fb4cde6dae31c53f13e9f0  ./docs/SEMANTIC_DIFFERENCES.md
 02e8a5b52b341390f008ff8bc62f5d2d982b23adb8b26cb73ef3b07dddeed807  ./docs/SOURCE_AUDIT.md
-1ce879d29924a6c8d1c507c6233879428e25b204c6645493b71c401e8a7fcc49  ./docs/STATUS.md
+4908edd6fcd6d559bfef07a60eb703b0382bd2e79f126ea8930fb4122d1df1b3  ./docs/STATUS.md
 9c2582c40fbd9a4e2b163abed784f5a6c82b2cb3136c37a4123a0ba6584f6136  ./docs/TAPEOUT.md
+e61e74c84bce2ec92ef18520eb134299f9341e63d3ec43cdbe0ef4879d22ba37  ./docs/ULX3S_SMOKE_AND_UART.md
 a08743f1a3cf4af68683cdaac5b00ca624ac875dbeef9f78614bda7297579df8  ./docs/USE_CASES.md
 20aa56b3f69c28c9639e9bd16b8239f0ef511d8fded9340185814b3257e25f01  ./docs/VALIDATION.md
 c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c  ./docs/semantics/reference/README.md
@@ -52,21 +53,37 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836  ./formal/gf128
 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f  ./formal/gf8_mul_formal.sv
 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e  ./formal/stream_alu_mul_pulse.sby
 b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1  ./formal/stream_alu_mul_pulse_formal.sv
+c463f7e5612c93ece40f4bb2163938757d03903de8eed1dd1b85529ea2d0b632  ./fpga/ulx3s/Makefile
+2193c115f54fc49c77280a544b0963bbff3cc5840fb5795fdf44e7dcb44f5781  ./fpga/ulx3s/build_smoke.sh
+da9ff87e6546086c402879bb6b0f3c21f7df2712c70ad103872462369e222381  ./fpga/ulx3s/build_uart.sh
+8243770de3fb1cb65f8ef0ee345addab105cf7e219d0c3be5cf009743e27f59f  ./fpga/ulx3s/smoke.config
+e9dc79a86095c3c4f9e9d531746ee51c57d301e6840386670b5837aed72062ae  ./fpga/ulx3s/smoke.ys
+cd4a528e8502a4761efa123743afd1f6e180681af3349f05c5777ee489a92689  ./fpga/ulx3s/smoke_top.sv
+b2226a0db5c80da4de9ab630caf40f42678cb15acd3fa2f4f661f5d101146931  ./fpga/ulx3s/uart_bridge.sv
+b51f1a3974e7ae32bcbf9c32716aa9eb7d205e46e158a3f535bac7c04a57f7de  ./fpga/ulx3s/uart_rx.sv
+27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9  ./fpga/ulx3s/uart_tx.sv
+76513d0e0245b1e212b71ad56fdafeaa0a9654535a665f977bee4ef41a5bbd8f  ./fpga/ulx3s/ulx3s_top.sv
+1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2  ./fpga/ulx3s/ulx3s_v318_smoke.lpf
 85af4e1517f0bec1e0d586690d29c93b58ae9d3095c22cb081d184f51f79cd62  ./fpga_harness/BOUNDARY.md
-a25abf613168eb6fa3c1d45ccfb26e9c7eadf95f8445616d6030cc038d4b867d  ./fpga_harness/BUILD_PLAN.md
-1904480b3c114a1edb2f33add69bf493017c206aeb572b307d83f73a8bc8ac6e  ./fpga_harness/INVENTORY.md
-a97901243c2eb074f5b43eb3b620bf3675cbd2ecd415d9a945dda1acc7499d80  ./fpga_harness/README.md
-10365c2a44923b680ff5c8a1069af89508ac94d895d07c618ebca609d9343375  ./fpga_harness/board_detect.py
+dad7d78465d3b8f339d22d79c0823e52dc587fba26272b4f6fd7ce6ed1de6201  ./fpga_harness/BUILD_PLAN.md
+5afe24acc0e398a66591f66ef62fb63ca300c2f925f9de828547e7e9ea8b302e  ./fpga_harness/INVENTORY.md
+c58d6e0e447f6da7ffc769899ba021e386d4effdd27a987bdb0ece8235f3ebac  ./fpga_harness/README.md
+a538a3b5e64df095b867eb23f77953be4ea021a5d755f45f13a7b9a8ed8e7ccb  ./fpga_harness/board_detect.py
 f00b4c8c96b74b20c75ebc0cd3cc042def53f39d9cf1d963435e9b2e8f96e176  ./fpga_harness/boundary_check.py
 ac042826f976c6e04c668613676b006743f487a463e2cd6a2ca14a5f31571502  ./fpga_harness/fixtures/ulx3s_full_visibility.json
 7571676d26daf04b94b9fadbdbc9740568ea92439ae0830f41a7567fdbd002a7  ./fpga_harness/host/__init__.py
 9192a6565a1e455bc0a2143bdf293bc201505e6a964a1ac38f2025874713bf36  ./fpga_harness/host/mincore_uart.py
 93dbd041aaec9b476b5b1da6b9fced4740967a779b7bd130544f4d93777c09bd  ./fpga_harness/rtl/lean_silicon_lsc1_pins.sv
+608b33eb1cc3f5d63216e7e3074b0635e5d00ba4914d45bba0f0759f011ead12  ./fpga_harness/test_artefact_provenance.py
+8a9679c14d7201984cf164741dc7c96599e8ce73b03f176e223bff593250cb95  ./fpga_harness/test_atomic_publish.py
 9a4439844c2bc2f486a470a3cbbad271f7d1df5bef9da103a2fd80e3a9d49071  ./fpga_harness/test_board_detect.py
 523c4171885c2a1621be25812b0ac283b7ce6272a19b2a60a5b7b4240ce9bdef  ./fpga_harness/test_boundary_check.py
+00b12cbb73f0054731dd8ed1f7d4d5646fbcffec4699cca8b54d340607edc3e4  ./fpga_harness/test_portable_build_support.py
+3f87f766a0b5dcde66bcce9b25b420c0993a1c789caf045f6c91472f033dbe16  ./fpga_harness/test_ulx3s_uart.py
 ee455920032996e22976f2ddba66233deb1d6c7a0c2052f07a5522a08650165b  ./fpga_harness/tests/__init__.py
 02666faf1c09b2e31f7b185707f9059b4e425e6f80c04517534583b41d5360a2  ./fpga_harness/tests/host_uart/__init__.py
 5f9dc24a932d06558761458da8c5926605f9ca37ae662e342dae0aef92823479  ./fpga_harness/tests/host_uart/test_mincore_uart.py
+20b18779647bb635239ad75a2ee36c9e83b3014ff0fd8fd13a9e7eb0aa3754d4  ./fpga_harness/ulx3s_uart.py
 1e70f22fc5e73c872a0a2c1b764d4c10ec4df9150b47c9d5a19b9a6183af593b  ./host/README.md
 a8294c47be51b34fd3d8f80499618218838d3dece1e3d6b06f8e704ee02ca25f  ./host/__init__.py
 8fb848653468cf64ecf26e1d7acf598fe30027630ebe1941ec8424ee2f0a6079  ./host/errors.py
@@ -95,7 +112,7 @@ d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29  ./lean/lakefil
 8e3538e0ab5f81a3ee04927d8838c8c674e0e112838b4b3ce87ec218143276af  ./lean/lean-toolchain
 d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5  ./planning/OWNERSHIP.md
 a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587  ./planning/milestones.yaml
-01e08410080741c1f164e3b7459ea15db5966cef6629bfeb2691175f269efd00  ./requirements.txt
+1625e15cb9fb79c40afc1ab30e2a3483f5158253b0cc34f0cf84970ebcb9c2e3  ./requirements.txt
 73c8c4939d05b6fd2367c8fc992e8386ee1b505499abfd1050b8286022589f9c  ./results/fpga-harness-inventory-20260725/README.md
 13c80bbee4874817634c3edcef6a6a687fd4e6d1d5412c026fe9b314388eeb7c  ./results/fpga-harness-inventory-20260725/fpga-boundary.log
 9a271f2a916b0b6ee6cecb2426f0b3206ef074578be55d9bc94f6f3fe3ab86aa  ./results/fpga-harness-inventory-20260725/fpga-boundary.status
@@ -253,13 +270,30 @@ c05bcfb6cfbeaa2f72eb031a986a37e6094ec430022d6cce911cf4fcedfb101a  ./results/seri
 42f3d4668a80ab3bf2a16915803d5a212bb299ca8800fa24dfc0f8baaa88c509  ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.log
 ceceba3b9bc693c4b5a87f799e91ee36f93c483dd32d6e32514eb2a3e02779ad  ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.status
 228b1eb2253fe285abf3f2d6cf6a7748661a11367433e17a8cef8832ea6068e4  ./results/serial-mul-byte-order-20260725/toolchain.txt
+0d617e2e80e8749ea5f1b0a48f2da7ddac62dcb5f8def09126d60971f26dbf36  ./results/ulx3s-smoke-uart-20260725/SHA256SUMS
+ecd004f3008420bdf304a9d8f1084202847f65836bafed2aef69b858db180628  ./results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt
+7b45b067f30eb0a477f2eea894f79b0694ee3dcfb78752c935a2aa13c2a53d51  ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt
+dbda64dd3a2c4985c6d2a98123daac73461e2cb4d1ffb18da445920d5f2fe19b  ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt
+353825c15c00249b61be316b86c75c664a9ee2142a99a14f58a5fe7190d31830  ./results/ulx3s-smoke-uart-20260725/nextpnr.log
+f76f35d01b2f93608843c292ad056158f5be23ca61b5e8d61898d4732f75cb85  ./results/ulx3s-smoke-uart-20260725/nextpnr_uart.log
+8243770de3fb1cb65f8ef0ee345addab105cf7e219d0c3be5cf009743e27f59f  ./results/ulx3s-smoke-uart-20260725/smoke.config
+0a2dcd734f194819b6483b6d5a7e394677eb30634760d46a62d4f5542cdec944  ./results/ulx3s-smoke-uart-20260725/smoke.svf
+e81003f252d7b36ca38a0e95c2be813ea383dd919c06d0d53c6b56326cbd3cc6  ./results/ulx3s-smoke-uart-20260725/timing.txt
+435e10f7f36b9eec93cc0f88c660c2bcb570e279465ef11455fa251a65df7fcb  ./results/ulx3s-smoke-uart-20260725/timing_uart.txt
+5be356b89eb518e7af532be06af0368c8831554db03db7787192310c99a1781e  ./results/ulx3s-smoke-uart-20260725/tool_versions.txt
+6b761d5b6c0e60e130a7bc81cbb9f491ae329a9175376bbdfd6b2f6b624da4b6  ./results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt
+eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51  ./results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit
+96eb9eda7421bac902eacaeced21eee0db9a80b8f2f2effdb52b515d68e0b2e3  ./results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit
+e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d  ./results/ulx3s-smoke-uart-20260725/yosys.log
+7d50c170f623ccc6911a48dd18455bc1011a2be335a9997c6d85355d0c72e63d  ./results/ulx3s-smoke-uart-20260725/yosys_uart.log
 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c  ./sim/__init__.py
 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c  ./sim/cycle_model.py
 3ebec652b76c20903fde598d748dbaff596cbc3f962f80ca23f30b31e1327da5  ./sim/lsc1_transaction.py
 12dd1aca968efeafb9ffa7015f849607c96fb6e14ad2aa8f65938dd254ef6f49  ./sim/model.py
 dee5dc820b96f24d4dbd752b17aaad3c8e025d519c043dfd1ab7c46be5600245  ./sim/packet_executor_model.py
 659496fd9f21edafb7c4c12500d9b623bd0ea063808dc9494053ad923102dc31  ./sim/protocol_contract.py
 33a0956687b75cb08d19e58a7da8fc4acf622e63795f1220f57a38bc6d2c4117  ./sim/scalar_step_oracle.py
+d14a3e8aed08ece9ce5d9ac4ddc2d29bf218dcb4626592a11ff63eb36fe454dc  ./sim/test_atomic_publish.py
 a2fda9c21da5f3301de411060ffbb644c08c4c5e4c103e036b3834e2922ce10a  ./sim/test_cycle_model.py
 e6b030e8b15a0a73764faa3eedfeb937c6d8e8080bb17bf495cae3085c8dce26  ./sim/test_host_runtime.py
 f1ab500117ae9d7a20a9258a32dbc7271b4d0ec5f57d3fc058ff426ba2289a40  ./sim/test_lsc1_protocol_doc.py
@@ -274,11 +308,13 @@ f3e038032b2f1c76b176651dd79b266976091f1215b7e617c194888e387ab5e5  ./src/leanvm_b
 bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b  ./src/leanvm_b_stream_alu.sv
 e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c  ./src/tt_um_leanvm_b_mincore.sv
 a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331  ./src/user_config.tcl
-a021052d2cc38de0bbd8994680d8a647c7e55e3a3f3c77f5098d0dce9a29e843  ./test/Makefile
+a66afe03d6bc6e5993a13206a70236f13b185765e9798dd6033e7279123d556c  ./test/Makefile
 fcfcaf4f52e98837efe8a505ae8271beb1a4659504672cd1617aec1f93506f27  ./test/packet_frontend/Makefile
 799f514bf69c23fdef237d0d9ff6f64381a55c4228532c6e60a0e07e6e008de8  ./test/packet_frontend/tb_lsc1_packet_frontend.sv
 d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077  ./test/tb_m2_scalar_controller.sv
 b78b938f396ae20d1fdccde99281430778a879808e60a35788b6fe044151329c  ./test/tb_stream_alu.sv
+1cdfef46a813dd43f5700b5e3ed7ec0bfb07e07403c82f8ac8fa4fb4dfbd0d55  ./test/tb_uart_bridge.sv
+e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a  ./tools/atomic_publish.py
 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79  ./tools/design_space.csv
 54dca27c0adde9d13728952216a7cb7027cabacb4742e5bb26f063613c05c557  ./tools/design_space.md
 63693e361330234c6ba3cbfff282f808cc9ffda85cb074ec1de1d7d1fb3954b5  ./tools/design_space.py
@@ -289,6 +325,8 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919  ./tools/frozen
 16a04bf83da566c67f35f43d46db71c464b9f08e60952cae9b51419b33ec65fe  ./tools/interface_consistency.py
 87bf0131d197add11cab19ba34e9278a16dddcc066e254ca77b3c28d46b9da4b  ./tools/lean_compiler_export.py
 13cda9f3b47fda14a1ea23b3e210212eacd7250ea15ffd1e1ac638ea0d5bff3a  ./tools/m2_rtl_differential.py
+737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326  ./tools/portable_build_support.py
 af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0  ./tools/repo_consistency.py
 8b848ef50be2f01f34cac16e44469a18e3b4c087a5d6434cae71d4919a446c6b  ./tools/rtl_state_count.py
+a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db  ./tools/source_provenance.py
 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d  ./tools/sv_smoke_check.py

docs/STATUS.md

@@ -11,7 +11,7 @@
 | lean_compiler integration | artifact exported from the frozen compiler; `hints`/`main_frame`/`witness`/`trace` are `pub(crate)` upstream | `tools/lean_compiler_export.py`, `docs/HOST_RUNTIME.md` section 4 |
 | Host vs frozen Rust comparison | final memory only, for the 12 cells the fixture run touched; `cycles` and every per-step field explicitly not compared | `tools/host_upstream_comparison.py`, `docs/HOST_RUNTIME.md` section 5 |
 | Full scalar semantics | not implemented | planned graph |
-| ULX3S harness bitstream | not implemented | pin contract only |
+| ULX3S harness bitstreams | source-built, archived; not hardware-validated | `docs/ULX3S_SMOKE_AND_UART.md`, `results/ulx3s-smoke-uart-20260725/` |
 | Tiny Tapeout PPA / official zkDSL validation | not run for LSC-1 | planned graph |
 | Full-controller SV-to-frozen-ISA theorem | not implemented | `docs/PROOF_BOUNDARIES.md` |
 | RTL-to-netlist equivalence | not implemented | `docs/PROOF_BOUNDARIES.md` |