CPU 2A03

CPU: the Ricoh 2A03 (6502 core)

Specification: docs/cpu-6502.md. Crate: crates/rustynes-cpu.

The 2A03's CPU is a 6502 without decimal mode. RustyNES implements it one cycle at a time: every opcode, including the unofficial and unstable ones, issues its reads, writes and dummy accesses on the cycle where the hardware does, because games and test ROMs can observe them (a dummy read of $2002 or $4015 has side effects).

Key points

• Cycle-level bus contract. The CPU talks to the rest of the console only through the rustynes_cpu::Bus trait. Each cycle is clocked in two halves around its access so the PPU is caught up first; see Scheduler.
• Interrupts. The bus exposes /NMI and /IRQ as levels. The CPU edge-detects NMI and masks and delays IRQ itself, polling at the points the hardware does, which is what the cpu_interrupts_v2 tests check.
• DMA. OAM DMA and DMC DMA halt the CPU only on a read cycle and run through one unified per-cycle engine on the bus (docs/scheduler.md). A 2A03 die-revision option for an unconfirmed DMA re-read is a documented frontier (ADR 0033).
• Optional overclock (v3.1.0). Nes::set_cpu_overclock multiplies CPU cycles per frame while keeping the APU, DMC and mapper timers at the stock rate. It is not hardware behaviour, is off by default, and is recorded in movies and checked by netplay.

How it is checked

The CPU is pinned by a zero-diff comparison against the Nintendulator nestest log, blargg's instruction, timing and interrupt suites, and the CPU sections of AccuracyCoin. Current results are in docs/STATUS.md; see also Testing-Strategy.