Issues

• Bug Report: Faulting access makes the non-cacheable access in front of it trap

  RoaLogic/RV12#81 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: Non-cacheable load returns cache data when the next access is cacheable

  RoaLogic/RV12#80 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: With the caches disabled PMP and PMA are not enforced

  RoaLogic/RV12#79 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: FENCE.TSO and FENCE or FENCE.I with nonzero reserved fields raise an illegal instruction

  RoaLogic/RV12#78 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: minstret reads miss older instructions still in the pipeline

  RoaLogic/RV12#77 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: S-mode writes to scounteren are ignored

  RoaLogic/RV12#76 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: Interrupt traps leave mtval unchanged instead of writing zero

  RoaLogic/RV12#75 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: CSRRS and CSRRC on mip copy the external SEIP line into the software SEIP bit

  RoaLogic/RV12#74 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: Reading mip right after writing SEIP returns the old SEIP

  RoaLogic/RV12#73 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: PMP TOR ranges use pmpaddr without the 2-bit shift

  RoaLogic/RV12#72 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: sstatus does not show or update mstatus.VS

  RoaLogic/RV12#71 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: mstatus.SD always reads zero even when VS is dirty

  RoaLogic/RV12#70 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: EBREAK writes the address of the previous load or store into mtval

  RoaLogic/RV12#69 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: mtval on an illegal instruction exception has bits 1 and 0 equal to 01 instead of 11

  RoaLogic/RV12#68 · Filter by author hakunahmattatah opened on Nov 11, 2026

• Bug Report: FENCE.I hangs when the data cache has no dirty line

  RoaLogic/RV12#67 · Filter by author ororomik opened on Nov 10, 2026

• Bug Report: After an instruction fetch bus error the first instructions of the trap handler are skipped

  RoaLogic/RV12#66 · Filter by author ororomik opened on Nov 10, 2026

• Bug Report: The wrapper ties PMP_CNT to zero so the PMP CSRs do not exist when PMP_CNT is 16

  RoaLogic/RV12#65 · Filter by author ororomik opened on Nov 10, 2026

• RV32: S/U-mode XLEN becomes 0 after an M-mode mstatus write

  RoaLogic/RV12#64 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Parcel queue shifts fetch status by 16 bits per parcel, raising a false page fault

  RoaLogic/RV12#63 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• MRET right after a faulting load corrupts mstatus.MPP

  RoaLogic/RV12#62 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• MUL/DIV behind a faulting load or store still retires

  RoaLogic/RV12#61 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Fetch-stage exception is lost when pre-decode stalls

  RoaLogic/RV12#60 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• URET does not raise an illegal instruction exception

  RoaLogic/RV12#59 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Instruction access fault writes the instruction bits to mtval

  RoaLogic/RV12#58 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• C.EBREAK does not raise a breakpoint exception

  RoaLogic/RV12#57 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026