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1. Harvard-Processor Harvard-Processor Public

   A parameterized multi-cycle Harvard architecture processor designed from the ground up in Verilog. Developed using a complete RTL design workflow including simulation, linting, synthesis, Sky130 te…

   Verilog

2. High-Performance-Adder-Architectures High-Performance-Adder-Architectures Public

   RTL implementations of high-performance 64-Bit adder architectures, exploring carry computation, synthesis, timing analysis, and PPA trade-offs with post synthesis GLS with selected architectures t…

   SystemVerilog

3. High-Performance-Multipliers High-Performance-Multipliers Public

   RTL implementations of high-performance 32-Bit multiplier architectures, exploring arithmetic datapaths, synthesis, timing analysis, PPA trade-offs with post-synthesis GLS and characterization of i…

   SystemVerilog

4. Gate-Level-Cybernetic-Classifier Gate-Level-Cybernetic-Classifier Public

   This project explores how adaptive behavior and learning-like dynamics can emerge from purely deterministic gate-level systems. It evolves from strict Boolean matching to score-based decision makin…

   Verilog 2

5. Artificial-Neuron Artificial-Neuron Public

   This project implements a basic McCulloch–Pitts artificial neuron. The current versions supports two binary inputs, a programmable threshold and inhibitory weights allowing it to emulate logic func…

   SystemVerilog

6. Assembler Assembler Public

   Built custom assembly language and Assembler for my custom-built Computing Machinery project as its software extension. Mapped machine-functionality to assembly capable of data-control, machine-con…

   Python 1