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[phase4][chipstar][l0-igba] cache zeKernelSetIndirectAccess per kernel

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pocl-cpu on: push 1

pre_job

Build and cache spirv-tools

Build and cache llvm-${{ matrix.llvm-version }}

cpp-linter on: push 4

cpp-linter

x86 Intel GPU CI on: pull_request 5

refuse-chipfft-chipblas-on-level-zero

chipstar-llvm22-native-release

build-and-test-libraries

build-and-test-libceed

unit-tests-llvm-20-debug

unit-tests-llvm-20-release

unit-tests-llvm-21-debug

unit-tests-llvm-21-release

unit-tests-llvm-22-translator-debug

unit-tests-llvm-22-translator-release

unit-tests-llvm-22-native-debug

macOS ARM64 CI on: pull_request 2

build-and-test (translator)

build-and-test (native)

Libraries Presubmit on: pull_request 2

build-and-test-libraries-pastrami

build-and-test-libraries-salami

rusticl AMD GPU CI on: pull_request 1

build-and-hipinfo

.github/workflows/check-unit-tests-arm.yml on: pull_request 1

unit-tests-llvm-18-release-salami

pocl-cpu on: pull_request 5

pre_job

Build and cache spirv-tools

Build and cache llvm-19

Build and cache pocl 7.1 (llvm-19)

Build and test chipStar on pocl 7.1 (llvm-19)