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ogar-vocab: mint 0xC6 Mmio domain — C64 founding tenant - #284

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AdaWorldAPI merged 2 commits into
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Aug 25, 2026
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ogar-vocab: mint 0xC6 Mmio domain — C64 founding tenant#284
AdaWorldAPI merged 2 commits into
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claude/c64-6502-falsifier-shztkk

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What

Mints the 0xC6XX domain: ConceptDomain::Mmio — memory-mapped hardware platform ontology. The slot is deliberate: C6, one hex digit short of the C64, the founding tenant (operator-directed, 2026-08-25 session; C6 verified free — 0xC5XX+ fell through to Unassigned, pinned in tests).

Four container-KIND slots, following the 0x08XX OCR precedent exactly ("class-level container kinds only; content stays in content stores"):

slot concept
0xC601 mmio_chip — a memory-mapped peripheral chip kind (VIC-II / SID / CIA / …)
0xC602 mmio_register — a register container kind; concrete registers are content rows keyed by address
0xC603 rom_image — resident ROM image kind (KERNAL / BASIC / chargen)
0xC604 machine_memory_map — the banking/overlay layout kind

The ~104 concrete VIC-II/SID/CIA registers and the 56 6502 mnemonics are content rows, never concept slots$D021 is data read through the ClassView, preserving C64-rs's hard rule ("JSR/LDA/$A9 are never their own classid").

Why beside C4, not inside it

BinaryLifting (0xC4) is the architecture-agnostic lift/IR ontology (program image, function, section, symbol). A border-colour register is a platform fact a lifted program references, not an IR concept — different vocabulary, different lifecycle, so a sibling domain. The C5 hole stays open by intent (same rule as the C2–C3 gap), pinned in the domain-routing test.

Provenance fence

Mirrors C4's fence, widened deliberately: MIT implementations (rust64) and vendor datasheets (6526/6567/6581 register facts) are lawful mint sources; GPL emulators (Frodo, zinc64, resid) stay behavioral/test-vector reference only — read, never transcribed.

Mechanics

  • enum variant + canonical_concept_domain arm + Unassigned-doc tail (0xC5XX, 0xC7XX+)
  • CODEBOOK rows, class_ids consts + ALL entries, 4 Class builders wired into all_promoted_classes()
  • both ALL.len() pins bumped 93 → 97 (lib.rs + capability_registry.rs — the second one caught by the test run, not by memory)
  • domain tests pin C600/C6FFMmio and the C500/C700 edges

Gates: cargo test -p ogar-vocab green (157 lib + doctests), clippy --all-targets clean, fmt clean, cargo check --workspace clean.

Follow-up (named, not hidden)

The lance-graph ogar_codebook mirror needs the same four rows before assert_codebook_parity consumers re-run against this vocab — that lands as its own lance-graph PR, per the 2026-08-14 fuse-removal design (drift surfaces in tests, not consumer builds).


Generated by Claude Code

New ConceptDomain::Mmio at 0xC6 (one hex digit short of the C64, the
deliberate slot choice — same naming move as C4's blast radius). Four
container-KIND slots per the 0x08XX OCR precedent: mmio_chip (0xC601),
mmio_register (0xC602), rom_image (0xC603), machine_memory_map (0xC604).
Concrete VIC-II/SID/CIA registers and the 6502 mnemonics stay CONTENT
rows — $D021 is data read through the ClassView, never a classid.

Provenance fence mirrors C4's, widened deliberately: MIT implementations
(rust64) and vendor datasheets are lawful mint sources; GPL emulators
remain behavioral reference only.

Both ALL-count pins bumped 93 -> 97; domain-routing tests pin C600/C6FF
and the C5/C7 edges (the C5 hole stays open by intent).

The lance-graph ogar_codebook mirror needs the same four rows before its
assert_codebook_parity consumer gate re-runs against this vocab — noted
here, landed as its own PR there.
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AdaWorldAPI marked this pull request as ready for review August 25, 2026 19:00
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AdaWorldAPI merged commit c02efa1 into main Aug 25, 2026
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