diff --git a/hw/top_chip/data/chip_testplan.hjson b/hw/top_chip/data/chip_testplan.hjson new file mode 100644 index 000000000..d5f0d8c58 --- /dev/null +++ b/hw/top_chip/data/chip_testplan.hjson @@ -0,0 +1,634 @@ +// Copyright lowRISC contributors (COSMIC project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "top_chip" + + // import_testplans: intentionally absent. Mocha has no chip-level per-IP testplan files yet. + // The IP-level testplans under hw/top_chip/ip, hw/top_chip/ip_autogen/ and hw/vendor/ are + // unit-level DV plans and should not be imported here. + // + // Firmware variants: a testpoint runs both the vanilla (non-CHERI) and the CHERI firmware image + // whenever its tests list names both. A single test name means one variant only. + + testpoints: [ + + /////////////////////////////////////////////////////////////////////////// + // Serial Interfaces: UART, SPI, I2C // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_uart_smoke + desc: '''Verify UART register reachability and TX/RX via the UART's internal loopback at the + chip level. + + SW configures the UART and enables its internal (system) loopback (`uart_loopback_set`), + which ties the TX path to the RX path inside the IP, then transmits the byte sequence + "Test String" character-by-character and reads each byte back, passing if every received + byte matches. Because system loopback keeps the data inside the IP (`uart_tx_o` stays + idle), this confirms register access and the internal TX/RX datapath but does not + exercise the chip pins; the external pin path is covered by chip_uart_tx_rx. The UVM + UART agent passively monitors the pins. + ''' + stage: V1 + tests: ["uart_smoke", + "uart_smoke_cheri"] + } + { + name: chip_uart_tx_rx + desc: '''Verify UART TX/RX over the chip pins using an agent-side loopback. + + SW configures the UART (baud rate and enables), confirming register reachability, and + transmits a byte sequence out `uart_tx_o` with no internal loopback. The UVM UART agent, + connected to the chip UART pins, receives each byte on `uart_tx_o` and drives it back + onto `uart_rx_i`, closing the loopback after the chip pins. SW reads each byte back and + passes if it matches what was sent. This exercises the real `uart_tx_o` / `uart_rx_i` + pin path and the agent, the integration-unique path that cannot be observed below the + chip level, and is the true chip-level UART smoke. + ''' + stage: V1 + tests: ["uart_tx_rx", + "uart_tx_rx_cheri"] + } + { + name: chip_spi_device_smoke + desc: '''Verify SPI device register reachability and a basic agent-driven SPI transaction + at the chip level. + + An SPI agent configured as an SPI host drives the chip spi_device pins. SW configures + the spi_device (including its JEDEC device ID), and writes then reads back a CSR + (walking 0x55555555 / 0xAAAAAAAA patterns) to confirm reachability via xbar_peri. The + agent then issues a simple flash command over the SPI pins that the device services + directly (for example Read JEDEC ID); the response observed by the agent is confirmed + to match the configured value. This exercises the external SPI pin path into the + spi_device, distinct from and lighter than the upload path in chip_spi_device_upload. + ''' + stage: V1 + tests: ["spi_device_smoke", + "spi_device_smoke_cheri"] + } + { + name: chip_spi_device_upload + desc: '''Verify SPI device upload path from an external SPI host to SW at the chip level. + ''' + stage: V2 + tests: ["spi_device_upload_test", + "spi_device_upload_test_cheri"] + } + { + name: chip_spi_host_smoke + desc: '''Verify SPI host TX and RX data integrity at the chip level. + + The testbench (`tb.sv`) wires `spi_host_sd_o[0]` (COPI) to `spi_host_sd_i[1]` + (CIPO) via a combinatorial assignment, creating a hardware loopback in standard + SPI mode. SW initialises the SPI host by writing its configuration registers + (`CONTROL`, `CONFIGOPTS`, `CSID`) and reads back a configuration register to confirm + reachability via xbar_peri. It then writes the 32-bit word 0xDEADC0DE, reads back one + word over the loopback, and passes if the received value matches. + ''' + stage: V1 + tests: ["spi_host_smoke", + "spi_host_smoke_cheri"] + } + { + name: chip_spi_host_tx_rx + desc: '''Verify SPI host TX and RX over the chip pins against an agent-driven external SPI + device (a proper transmit test, beyond the tb loopback smoke). + ''' + stage: V2 + tests: ["spi_host_tx_rx", + "spi_host_tx_rx_cheri"] + } + { + name: chip_i2c_host_tx_rx + desc: '''Verify I2C controller-mode TX and RX at the chip level. + + The DV I2C agent is configured as a target-mode responder. SW configures the I2C + block in controller mode by writing its timing configuration registers, which also + confirms register reachability via xbar_peri. SW then drives a write transfer + followed by a read-back transfer against the agent. The number of bytes per transfer + and the 7-bit target address are randomized (the byte count is constrained to the + TX/RX FIFO depth) and the payload is a walking-ones pattern. The test passes when + every byte read back matches the byte written, confirming an agent-driven + controller-mode transaction over the chip I2C pins in both directions. + ''' + stage: V1 + tests: ["i2c_host_tx_rx", + "i2c_host_tx_rx_cheri"] + } + { + name: chip_i2c_device_tx_rx + desc: '''Verify I2C target-mode RX and TX at the chip level. + + The DV I2C agent is configured as a controller-mode initiator and issues write and + read transfers to the I2C block operating in target mode. The transfer address (one + of two randomized target addresses) and the number of bytes per transfer are + randomized. SW services each transfer and compares the bytes exchanged in every + transfer at the end. The test passes when all transactions complete without error and + the data matches, confirming target-mode connectivity and data flow in both + directions. Because the target-mode SW must load its TX FIFO before the host agent + reads it, the vseq waits on a SW-to-DV signal that the FIFO is ready before issuing the + read transfer. + ''' + stage: V1 + tests: ["i2c_device_tx_rx", + "i2c_device_tx_rx_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // GPIO // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_gpio_smoke + desc: '''Verify GPIO output drive and input sample at the chip level. + + SW enables all 32 GPIO pins as outputs (`GPIO_REG_DIRECT_OE = 0xFFFFFFFF`) and + drives a walking-ones pattern across all pins. After the last pin, output enables + are cleared to allow the pads to be driven externally. The UVM vseq monitors pin + values via `gpio_vif` and waits for each expected walking-1 pattern using + `DV_SPINWAIT`. Once output enables are cleared (pins go to Z), the vseq drives + 0x55555555 onto the GPIO input pads. SW polls `GPIO_REG_DATA_IN` for this + pattern and passes when it is observed. + ''' + stage: V1 + tests: ["gpio_smoke", + "gpio_smoke_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // ROM Control // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_rom_ctrl_smoke + desc: '''Verify that the CPU can boot from ROM and execute a software image in SRAM. + + A minimal SW image is loaded into SRAM via backdoor. The ROM (`mem_init_file.vmem`) + runs its startup sequence and transfers control to the SRAM image. The test passes + when the SW image reports completion via the sim_sram SW test status interface. + ''' + stage: V1 + tests: ["rom_ctrl_smoke", + "rom_ctrl_smoke_cheri"] + } + { + name: chip_rom_ctrl_integrity_check + desc: '''Verify that the ROM controller performs and signals a correct integrity check + before releasing the CPU from reset. + ''' + stage: V2 + tests: ["rom_ctrl_integrity_check"] + } + + /////////////////////////////////////////////////////////////////////////// + // System Management: Clock, Reset, Power // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_clkmgr_smoke + desc: '''Verify software control of gateable and hintable clocks via the clock manager. + + Two sub-tests: + - Gateable clock: reads the current enable state of `CLKMGR_GATEABLE_CLOCK_IO_PERI`, + toggles it, reads back to confirm the change, then restores and re-confirms. + - Hintable clock: same read-toggle-verify-restore sequence for + `CLKMGR_HINTABLE_CLOCK_MAIN`; also checks that when the hint is set the clock + enabled status reflects it. + + Note: in Mocha both of these clocks (`clk_io_peri` and `clk_main_hint`) drive nothing + and are tied into `unused_manager_output` in top_chip_system.sv, so the scope here is the + register interface only. If the clocks are removed, this testpoint goes with them. + ''' + stage: V1 + tests: ["clkmgr_smoke", + "clkmgr_smoke_cheri"] + } + { + name: chip_rstmgr_smoke + desc: '''Verify the software-requested reset path through the reset manager. + + On the first boot (POR cause), SW reads the reset cause register, clears the POR + bit, and requests a software reset via `rstmgr_software_reset_request`. On the + second boot (SW reset cause), SW reads the register, confirms + `RSTMGR_RESET_INFO_SW_RESET` is set, clears it, and signals pass. Any other reset + cause sequence is a failure. + ''' + stage: V1 + tests: ["rstmgr_smoke", + "rstmgr_smoke_cheri"] + } + { + name: chip_pwrmgr_smoke + desc: '''Verify power manager CSR accessibility and reset-state correctness. + + Three sub-tests: + - Control register: confirms reset value contains only `MAIN_PD_N`, writes + `LOW_POWER_HINT | CORE_CLK_EN | IO_CLK_EN`, syncs (`pwrmgr_cfg_sync`), reads + back, then restores and re-confirms. + - Wakeup enable register: confirms reset value is 0, writes + `SOC_PROXY_EXT_WKUP_REQ`, syncs, reads back, clears, and re-confirms. + - Status registers: confirms `WAKEUP_STATUS`, `RESET_STATUS`, + `ESCALATE_RESET_STATUS`, and `WAKE_INFO` are all 0 at reset, then clears + `WAKE_INFO` and confirms it remains 0. + ''' + stage: V1 + tests: ["pwrmgr_smoke", + "pwrmgr_smoke_cheri"] + } + + { + name: chip_pwrmgr_wakeup + desc: '''Verify low-power entry and wakeup sequence through the power manager. + ''' + stage: V2 + tests: ["pwrmgr_wakeup_test", + "pwrmgr_wakeup_test_cheri"] + } + { + name: chip_pwrmgr_lowpower_quiescent + desc: '''Verify that the clocks which must stop in low-power are quiescent while the + always-on clocks keep running, at the chip level. + ''' + stage: V2 + tests: ["pwrmgr_lowpower_quiescent_test", + "pwrmgr_lowpower_quiescent_test_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // Interrupt Infrastructure: RV_PLIC, RV_TIMER // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_rv_plic_smoke + desc: '''Verify PLIC register access and end-to-end interrupt routing to the CPU. + + Three sub-tests run in sequence: + - Register R/W: writes and reads back priority and interrupt-enable registers for + both machine and supervisor privilege modes. + - Machine-mode IRQ: configures PLIC priority and threshold, enables the UART + interrupt, SW-forces `uart_intr_rx_frame_err`, polls until MIP.MEIP asserts, + claims the interrupt ID via PLIC, clears the UART interrupt, completes the + claim, and confirms MIP.MEIP de-asserts. + - Supervisor-mode IRQ: same full claim/complete cycle using `uart_intr_rx_timeout` + and MIP.SEIP. + ''' + stage: V1 + tests: ["rv_plic_smoke", + "rv_plic_smoke_cheri"] + } + { + name: chip_rv_plic_all_irqs + desc: '''Verify end-to-end interrupt routing from every PLIC-connected IP to the CPU + (TOP_INTERRUPT_ROUTING). + ''' + stage: V2 + tests: ["rv_plic_all_irqs_test", + "rv_plic_all_irqs_test_cheri"] + } + { + name: chip_rv_plic_priority + desc: '''Verify PLIC priority arbitration with simultaneous interrupt sources at the chip level. + ''' + stage: V2 + tests: ["rv_plic_priority_test", + "rv_plic_priority_test_cheri"] + } + { + name: chip_rv_timer_smoke + desc: '''Verify RV timer counter accuracy and interrupt-pending flag delivery. + + Two sub-tests: + - Accuracy test: schedules the timer 100 μs in the future, enables its interrupt, + and uses the hart cycle counter to confirm the interrupt-pending flag is clear + before 90 μs and set after 110 μs (±10 μs tolerance around the target). + - IRQ pending test: schedules the timer 50 μs out, enables the interrupt, and + verifies MIP.MTIP was clear before expiry and set after the timer fires. + ''' + stage: V1 + tests: ["rv_timer_smoke", + "rv_timer_smoke_cheri"] + } + { + name: chip_rv_timer_irq + desc: '''Verify preemptable machine-mode timer interrupt delivery end-to-end. + + SW globally enables interrupts, enables the machine-timer interrupt at the hart, + and runs 10 back-to-back iterations: schedules the timer 100 μs out, then blocks + with `WAIT_FOR_CONDITION_PREEMPTABLE` until `interrupt_handled` is set. The trap + handler clears the timer by scheduling infinitely far ahead and sets the flag. + A failure in any of the 10 iterations fails the test. + ''' + stage: V2 + tests: ["rv_timer_irq", + "rv_timer_irq_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // Debug: RV_DM // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_rv_dm_smoke + desc: '''Verify JTAG-to-debug-module connectivity and basic hart control at the chip level. + + A JTAG agent connected to the chip JTAG pins reads the DTM IDCODE + (jtag_id_pkg::RV_DM_JTAG_IDCODE) and activates the debug module (dmcontrol.dmactive), + then reads dmstatus and hartinfo to confirm the single hart is visible. It requests a + halt (dmcontrol.haltreq) and confirms the hart halts (dmstatus.allhalted), which also + confirms dm_top.debug_req_o reaches the CVA6-CHERI hart. With the hart halted it reads + a GPR via an abstract command (exercising the debug-memory device-side port through + which the halted hart runs the debug ROM), then resumes and confirms dmstatus.allrunning. + + This exercises the integration-unique path from the JTAG TAP through the DMI + (dmi_jtag) and dm_top to the CPU, which cannot be observed below the chip level. + + CHERI note: CVA6-CHERI disables all CHERI checks while in debug mode, so debug-ROM fetch + and abstract commands are not subject to PCC bounds (no debug-mode fetch-bounds + testpoint is needed). Abstract register access currently transfers 64-bit data only, + with no capability tag; full-capability readout including tag is an RC-1 item tracked by + chip_rv_dm_cap_reg_access. + ''' + stage: V1 + tests: ["rv_dm_smoke", + "rv_dm_smoke_cheri"] + } + { + name: chip_rv_dm_ndm_reset + desc: '''Verify that the debug module can issue a non-debug-module (NDM) reset via JTAG DMI + and remains accessible throughout. + ''' + stage: V2 + tests: ["rv_dm_ndm_reset_req", + "rv_dm_ndm_reset_req_cheri", + "rv_dm_ndm_reset_req_when_cpu_halted", + "rv_dm_ndm_reset_req_when_cpu_halted_cheri"] + } + { + name: chip_rv_dm_sba + desc: '''Verify debug-module System Bus Access (SBA) to chip memory at the chip level. + ''' + stage: V2 + tests: ["rv_dm_sba_access", + "rv_dm_sba_access_cheri"] + } + { + name: chip_rv_dm_access_after_wakeup + desc: '''Verify that the debug module is inaccessible during low power and restored after + wakeup, at the chip level. + ''' + stage: V2 + tests: ["rv_dm_access_after_wakeup", + "rv_dm_access_after_wakeup_cheri"] + } + { + name: chip_rv_dm_cap_reg_access + desc: '''Verify full CHERI capability readout from the core to the debug module (RC-1). + ''' + stage: V2 + tests: ["rv_dm_cap_reg_access_test_cheri"] + } + + + /////////////////////////////////////////////////////////////////////////// + // Mailbox // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_mailbox_smoke + desc: '''Verify Mailbox FIFO operation and interrupt delivery at the chip level. + + SW flushes both FIFOs, acknowledges any pending interrupts, sets threshold + registers to `MAILBOX_FIFO_DEPTH`, enables all three interrupts, then: + - Confirms the read FIFO is empty and write FIFO is not full. + - Writes `MAILBOX_FIFO_DEPTH` elements (0xBEEF0000..N) and confirms the write + FIFO is full with only the w_full interrupt pending. + - Flushes both FIFOs, acknowledges w_full, and re-confirms the write FIFO is + empty with no pending interrupts. + ''' + stage: V1 + tests: ["mailbox_smoke", + "mailbox_smoke_cheri"] + } + + { + name: chip_mailbox_ext_tx_rx + desc: '''Verify bidirectional mailbox message passing between the external AXI port and + the CPU at the chip level. + ''' + stage: V2 + tests: ["mailbox_ext_tx_rx_test", + "mailbox_ext_tx_rx_test_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // Entropy Source and KMAC // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_entropy_src_smoke + desc: '''Verify entropy source basic operation and accessibility at the chip level. + + SW reads the entropy source health-test configuration registers to confirm the IP + is reachable via xbar_peri, then switches to firmware-override mode and reads + entropy words directly from the SW FIFO. The test passes when the expected number + of valid entropy words are returned, confirming the hardware noise input is + connected and the IP produces output. + ''' + stage: V1 + tests: ["entropy_src_smoke", + "entropy_src_smoke_cheri"] + } + { + name: chip_kmac_rom_app + desc: '''Verify the KMAC application interface used by the ROM controller for boot-time + integrity checking. + ''' + stage: V2 + tests: ["kmac_rom_app_test"] + } + + /////////////////////////////////////////////////////////////////////////// + // Tag Controller // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_tag_ctrl_smoke + desc: '''Verify tag controller CSR accessibility and basic tag-tracking at the chip level. + + SW reads and writes the tag controller configuration registers to confirm the block + is reachable via the memory map. SW then performs a capability store to a + tag-tracked memory region, reads back the tag bit via the tag controller interface, + and confirms it is set. A subsequent sub-word write to the same slot is confirmed + to clear the tag. Verifies the tag controller is correctly integrated and its + AXI tag-tracking path is functional end-to-end. + ''' + stage: V1 + tests: ["tag_ctrl_smoke", + "tag_ctrl_smoke_cheri"] + } + + { + name: chip_tag_ctrl_dram + desc: '''Verify CHERI capability tag tracking through the tag controller for DRAM accesses + at the chip level. + + The UVM environment models the DRAM interface (`dram_req_o` / `dram_resp_i`). SW + stores capabilities to DRAM addresses at varying alignments using `csc`, then loads + them back with `clc` and confirms the tag bit is set via `gctag`. A sub-word write + to a capability slot is confirmed to clear only that slot's tag while leaving + adjacent slots intact. The test exercises enough distinct cache lines to provoke at + least one tag-cache eviction and refill, confirming tag state is preserved across + evictions. Verifies the tag controller AXI pipeline and tag cache are correctly + integrated end-to-end at the chip level. + + CHERI firmware only. + ''' + stage: V2 + tests: ["tag_ctrl_dram_test_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // AXI SRAM // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_axi_sram_smoke + desc: '''Verify AXI SRAM read/write data integrity with back-to-back 64-bit accesses. + + SW uses inline assembly to issue 8 consecutive 64-bit stores of known values + (0xB037...-0x0E91...) immediately followed by 8 64-bit loads, then compares each + loaded value to the stored value. In CHERI mode (`__riscv_zcherihybrid`) capability + registers (`ct0`) with `csc`/`clc` are used; in vanilla mode plain `t0`/`sd`/`ld` + are used. The tight store-load sequence stresses AXI pipeline buffering. + ''' + stage: V1 + tests: ["axi_sram_smoke", + "axi_sram_smoke_cheri"] + } + { + name: chip_axi_sram_tag + desc: '''Verify CHERI capability tag storage and per-slot invalidation in AXI SRAM. + + SW uses CHERI inline assembly (`csc`/`clc`/`gctag`) to exercise the tag controller + across three scenarios: + - Tags start unset; storing valid capabilities sets them; a sub-word write (word, + byte, half-word, or double) to a capability slot clears only that slot's tag + while leaving adjacent slots intact. + - Storing a null capability (`csc cnull`) clears the tag; a sub-word write to the + most-significant word of a slot also clears it. + - Half-word and byte writes to the most-significant part of a slot invalidate only + that slot, leaving others unchanged. + In vanilla (non-CHERI) mode the test body is a no-op and returns true. + ''' + stage: V2 + tests: ["axi_sram_tag_test", + "axi_sram_tag_test_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // AXI Crossbar // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_axi_xbar_smoke + desc: '''Verify AXI crossbar address decoding and routing to all AXI devices at the + chip level. + + SW issues write-then-read-back transactions to a representative address within + each CPU-accessible AXI device region: SRAM, ROM control memory (read), and + Mailbox. Routing to the dedicated SW-DV window device (SwDvWindow, base 0x2002_0000) + is also confirmed by reading its read-only HW_ID register and checking the expected + value, since that window is a DV sink rather than general memory. The DRAM port + (routed through the tag controller) and the RestOfChip passthrough (Ethernet, FPGA + only) are not exercised here. Each transaction is confirmed to reach the correct + device by verifying the read-back value matches the written value and no bus error is + signalled. In CHERI mode, capability-tagged accesses are also routed through the + crossbar. Verifies the AXI crossbar address-decode map (8 device ports) is complete + and correctly connected in the top-level integration. + ''' + stage: V1 + tests: ["axi_xbar_smoke", + "axi_xbar_smoke_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // TileLink Crossbar // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_tl_xbar_smoke + desc: '''Verify TileLink crossbar (xbar_peri) address decoding and routing to all + TL-UL peripheral devices at the chip level. + + SW reads a read-only status or identification register from each of the twelve + peripherals connected to xbar_peri: UART, SPI host, SPI device, I2C, GPIO, + clock manager, reset manager, power manager, PLIC, timer, entropy source, + and ROM control registers. A non-zero or expected-value response confirms the + crossbar routes each access to the correct device. A bus error or an all-zero + response to a register with a non-zero reset value is a failure. Verifies the + TileLink crossbar address-decode map is complete and correctly connected in the + top-level integration. + ''' + stage: V1 + tests: ["tl_xbar_smoke", + "tl_xbar_smoke_cheri"] + } + + /////////////////////////////////////////////////////////////////////////// + // Test Framework // + /////////////////////////////////////////////////////////////////////////// + + { + name: chip_test_framework_smoke + desc: '''Verify the DV test framework and the SW-to-DV communication path that underlie all + firmware-driven tests. + + A minimal firmware image writes a known log message to `SW_DV_LOG_ADDR` and the pass + token to `SW_DV_TEST_STATUS_ADDR`. These addresses live in the dedicated SW-DV window + (sim_sram_axi at 0x2002_0000, its own AXI crossbar device SwDvWindow) - not the chip + SRAM or DRAM. The UVM testbench confirms the `sim_sram_axi_sink` intercepts the AXI + write, drives `sw_test_status_vif.sw_test_done`, and the logged message is captured + correctly. SW also reads the read-only `HW_ID` register in the window and confirms it + matches the expected platform id (HwIdSimUvm). Validates the full SW to sim_sram_axi to + sw_test_status_if to UVM path as a standalone check rather than relying on it + implicitly in every other test. + ''' + stage: V1 + tests: ["test_framework_test", + "test_framework_test_cheri"] + } + { + name: chip_test_framework_dv_log + desc: '''Verify the SW-to-DV logging path used by the firmware tests. + + SW emits log messages through the `log` register in the SW-DV window. The testbench + decodes each one against the message database extracted from the image at build time, + and confirms a known sequence of messages arrives in order, each decoding to the + expected text, covering a plain message and a printf-style message whose arguments are + formatted from the values SW passed. Only the format identifier and the arguments cross + the window, so the message text stays out of the image and off the UART. + ''' + stage: V1 + tests: ["dv_log_smoketest", + "dv_log_smoketest_cheri"] + } + { + name: chip_test_framework_exception + desc: '''Verify that the DV test framework exception handler correctly identifies and + skips over illegal instructions. + + SW deliberately executes two `unimp` instructions: a 4-byte encoding (tval = + 0xC0001073) and a 2-byte compressed encoding (tval = 0x0000). The exception handler + intercepts each illegal-instruction trap (cause = 2), inspects `tval` to determine + the instruction width, advances `epc` by 4 or 2 accordingly, and returns. The test + passes if SW resumes execution after both `unimp` instructions and reaches the + final `return true`. + ''' + stage: V1 + tests: ["test_framework_exception_test", + "test_framework_exception_test_cheri"] + } + + ] +} diff --git a/hw/top_chip/dv/top_chip_sim_cfg.hjson b/hw/top_chip/dv/top_chip_sim_cfg.hjson index 1a712326d..4a5ed0234 100644 --- a/hw/top_chip/dv/top_chip_sim_cfg.hjson +++ b/hw/top_chip/dv/top_chip_sim_cfg.hjson @@ -19,7 +19,7 @@ fusesoc_core: lowrisc:mocha_dv:top_chip_sim:0.1 // Testplan hjson file. - testplan: "" + testplan: "{self_dir}/../data/chip_testplan.hjson" // Import additional common sim cfg files. import_cfgs: [ @@ -45,90 +45,59 @@ // List of test specifications. tests: [ { - name: uart_smoke - uvm_test_seq: top_chip_dv_uart_base_vseq - sw_images: ["uart_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_vanilla.vmem", - "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] - } - { - name: uart_smoke_cheri - uvm_test_seq: top_chip_dv_uart_base_vseq - sw_images: ["uart_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_cheri.vmem", - "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] - - } - { - name: rv_plic_smoke - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["plic_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_vanilla.vmem", - "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] - - } - { - name: rv_plic_smoke_cheri - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["plic_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_cheri.vmem", - "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] - - } - { - name: rv_timer_smoke + name: axi_sram_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_vanilla.vmem", + sw_images: ["axi_sram_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: rv_timer_smoke_cheri + name: axi_sram_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_cheri.vmem", + sw_images: ["axi_sram_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: rv_timer_irq + name: axi_sram_tag_test uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_interrupt_test_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_vanilla.vmem", + sw_images: ["axi_sram_tag_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: rv_timer_irq_cheri + name: axi_sram_tag_test_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_interrupt_test_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_cheri.vmem", + sw_images: ["axi_sram_tag_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: test_framework_test + name: axi_xbar_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_test_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_test_vanilla.vmem", + sw_images: ["axi_xbar_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_xbar_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: test_framework_test_cheri + name: axi_xbar_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_test_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_test_cheri.vmem", + sw_images: ["axi_xbar_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_xbar_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: test_framework_exception_test + name: clkmgr_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_exception_test_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_vanilla.vmem", + sw_images: ["clkmgr_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: test_framework_exception_test_cheri + name: clkmgr_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_exception_test_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_cheri.vmem", + sw_images: ["clkmgr_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { @@ -146,31 +115,45 @@ "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: spi_device_smoke + name: entropy_src_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_device_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_vanilla.vmem", + sw_images: ["entropy_src_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: spi_device_smoke_cheri + name: entropy_src_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_device_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_cheri.vmem", + sw_images: ["entropy_src_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: spi_host_smoke - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_host_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_vanilla.vmem", + name: gpio_smoke + uvm_test_seq: top_chip_dv_gpio_smoke_vseq + sw_images: ["gpio_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: spi_host_smoke_cheri - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_host_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_cheri.vmem", + name: gpio_smoke_cheri + uvm_test_seq: top_chip_dv_gpio_smoke_vseq + sw_images: ["gpio_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: i2c_device_tx_rx + uvm_test_seq: top_chip_dv_i2c_device_tx_rx_vseq + sw_images: ["i2c_device_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_device_tx_rx_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: i2c_device_tx_rx_cheri + uvm_test_seq: top_chip_dv_i2c_device_tx_rx_vseq + sw_images: ["i2c_device_tx_rx_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_device_tx_rx_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { @@ -188,24 +171,80 @@ "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: i2c_device_tx_rx - uvm_test_seq: top_chip_dv_i2c_device_tx_rx_vseq - sw_images: ["i2c_device_tx_rx_test_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_device_tx_rx_test_vanilla.vmem", + name: kmac_rom_app_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["kmac_rom_app_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/kmac_rom_app_test_vanilla.vmem", + "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"] + } + { + name: mailbox_ext_tx_rx_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["mailbox_ext_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_ext_tx_rx_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: gpio_smoke - uvm_test_seq: top_chip_dv_gpio_smoke_vseq - sw_images: ["gpio_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_vanilla.vmem", + name: mailbox_ext_tx_rx_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["mailbox_ext_tx_rx_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_ext_tx_rx_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: gpio_smoke_cheri - uvm_test_seq: top_chip_dv_gpio_smoke_vseq - sw_images: ["gpio_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_cheri.vmem", + name: mailbox_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["mailbox_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: mailbox_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["mailbox_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_lowpower_quiescent_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_lowpower_quiescent_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_lowpower_quiescent_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_lowpower_quiescent_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_lowpower_quiescent_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_lowpower_quiescent_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_wakeup_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_wakeup_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_wakeup_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: pwrmgr_wakeup_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["pwrmgr_wakeup_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_wakeup_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { @@ -244,31 +283,26 @@ "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: clkmgr_smoke - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["clkmgr_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_vanilla.vmem", - "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] - } - { - name: clkmgr_smoke_cheri - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["clkmgr_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_cheri.vmem", + name: rv_dm_access_after_wakeup + uvm_test_seq: top_chip_dv_rv_dm_access_after_wakeup_vseq + sw_images: ["rv_dm_access_after_wakeup_test_vanilla:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_wakeup_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: pwrmgr_smoke - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["pwrmgr_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_vanilla.vmem", + name: rv_dm_access_after_wakeup_cheri + uvm_test_seq: top_chip_dv_rv_dm_access_after_wakeup_vseq + sw_images: ["rv_dm_access_after_wakeup_test_cheri:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_wakeup_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: pwrmgr_smoke_cheri - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["pwrmgr_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_cheri.vmem", + name: rv_dm_cap_reg_access_test_cheri + uvm_test_seq: top_chip_dv_rv_dm_cap_reg_access_vseq + sw_images: ["rv_dm_cap_reg_access_test_cheri:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", "+ChipMemDRAM_image_file={run_dir}/rv_dm_cap_reg_access_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { @@ -279,6 +313,14 @@ "+ChipMemDRAM_image_file={run_dir}/rv_dm_ndm_reset_req_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } + { + name: rv_dm_ndm_reset_req_cheri + uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_vseq" + sw_images: ["rv_dm_ndm_reset_req_test_cheri:5" "bootrom:5"] + run_opts: ["+en_scb_tl_err_chk=0", "+use_jtag_dmi=1", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_ndm_reset_req_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } { name: rv_dm_ndm_reset_req_when_cpu_halted uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_when_cpu_halted_vseq" @@ -288,176 +330,390 @@ "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: rv_dm_access_after_wakeup - uvm_test_seq: top_chip_dv_rv_dm_access_after_wakeup_vseq - sw_images: ["rv_dm_access_after_wakeup_test_vanilla:5" "bootrom:5"] + name: rv_dm_ndm_reset_req_when_cpu_halted_cheri + uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_when_cpu_halted_vseq" + sw_images: ["rv_dm_ndm_reset_req_when_cpu_halted_test_cheri:5" "bootrom:5"] run_opts: ["+use_jtag_dmi=1", - "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_wakeup_test_vanilla.vmem", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_ndm_reset_req_when_cpu_halted_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: rv_dm_access_after_escalation_reset - uvm_test_seq: "top_chip_dv_rv_dm_access_after_escalation_reset_vseq" - sw_images: ["rv_dm_access_after_escalation_reset_test_vanilla:5" "bootrom:5"] - run_opts: ["+use_jtag_dmi=1", - "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_escalation_reset_test_vanilla.vmem", + name: rv_dm_sba_access + uvm_test_seq: top_chip_dv_rv_dm_sba_access_vseq + sw_images: ["rv_dm_sba_access_test_vanilla:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", "+ChipMemDRAM_image_file={run_dir}/rv_dm_sba_access_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: mailbox_smoke - uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["mailbox_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_vanilla.vmem", + name: rv_dm_sba_access_cheri + uvm_test_seq: top_chip_dv_rv_dm_sba_access_vseq + sw_images: ["rv_dm_sba_access_test_cheri:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", "+ChipMemDRAM_image_file={run_dir}/rv_dm_sba_access_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: mailbox_smoke_cheri + name: rv_dm_smoke + uvm_test_seq: top_chip_dv_rv_dm_smoke_vseq + sw_images: ["rv_dm_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", "+ChipMemDRAM_image_file={run_dir}/rv_dm_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: rv_dm_smoke_cheri + uvm_test_seq: top_chip_dv_rv_dm_smoke_vseq + sw_images: ["rv_dm_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+use_jtag_dmi=1", "+ChipMemDRAM_image_file={run_dir}/rv_dm_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: rv_plic_all_irqs_test uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["mailbox_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_cheri.vmem", + sw_images: ["rv_plic_all_irqs_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rv_plic_all_irqs_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: axi_sram_smoke + name: rv_plic_all_irqs_test_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_vanilla.vmem", + sw_images: ["rv_plic_all_irqs_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rv_plic_all_irqs_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: axi_sram_smoke_cheri + name: rv_plic_priority_test uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_cheri.vmem", + sw_images: ["rv_plic_priority_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rv_plic_priority_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: axi_sram_tag_test + name: rv_plic_priority_test_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_tag_test_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_vanilla.vmem", + sw_images: ["rv_plic_priority_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rv_plic_priority_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { - name: axi_sram_tag_test_cheri + name: rv_plic_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_tag_test_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_cheri.vmem", + sw_images: ["plic_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } { - name: entropy_src_smoke + name: rv_plic_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["entropy_src_smoketest_vanilla:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_vanilla.vmem", + sw_images: ["plic_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } { - name: entropy_src_smoke_cheri + name: rv_timer_irq uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["entropy_src_smoketest_cheri:5" "bootrom:5"] - run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_cheri.vmem", + sw_images: ["timer_interrupt_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } - ] - - // List of regressions. - regressions: [ { - name: smoke - tests: [ - "uart_smoke", - "uart_smoke_cheri", - "rv_plic_smoke", - "rv_plic_smoke_cheri", - "rv_timer_smoke", - "rv_timer_smoke_cheri", - "rv_timer_irq", - "rv_timer_irq_cheri", - "test_framework_test", - "test_framework_test_cheri", - "test_framework_exception_test", - "test_framework_exception_test_cheri", + name: rv_timer_irq_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["timer_interrupt_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: rv_timer_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["timer_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: rv_timer_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["timer_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_device_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_device_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_device_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_device_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_device_upload_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_device_upload_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_upload_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_device_upload_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_device_upload_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_upload_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_host_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_host_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_host_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["spi_host_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_host_tx_rx + uvm_test_seq: top_chip_dv_spi_host_tx_rx_vseq + sw_images: ["spi_host_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_tx_rx_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: spi_host_tx_rx_cheri + uvm_test_seq: top_chip_dv_spi_host_tx_rx_vseq + sw_images: ["spi_host_tx_rx_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_tx_rx_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: tag_ctrl_dram_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["tag_controller_tag_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/tag_controller_tag_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: tag_ctrl_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["tag_controller_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/tag_controller_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: tag_ctrl_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["tag_controller_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/tag_controller_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: test_framework_exception_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["test_framework_exception_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: test_framework_exception_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["test_framework_exception_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: test_framework_test + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["test_framework_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: test_framework_test_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["test_framework_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: tl_xbar_smoke + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["tl_xbar_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/tl_xbar_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: tl_xbar_smoke_cheri + uvm_test_seq: top_chip_dv_base_vseq + sw_images: ["tl_xbar_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/tl_xbar_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: uart_smoke + uvm_test_seq: top_chip_dv_uart_base_vseq + sw_images: ["uart_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: uart_smoke_cheri + uvm_test_seq: top_chip_dv_uart_base_vseq + sw_images: ["uart_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + + } + { + name: uart_tx_rx + uvm_test_seq: top_chip_dv_uart_base_vseq + sw_images: ["uart_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_tx_rx_test_vanilla.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + { + name: uart_tx_rx_cheri + uvm_test_seq: top_chip_dv_uart_base_vseq + sw_images: ["uart_tx_rx_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_tx_rx_test_cheri.vmem", + "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: [ + "axi_sram_smoke", + "axi_sram_smoke_cheri", + "axi_xbar_smoke", + "axi_xbar_smoke_cheri", + "clkmgr_smoke", + "clkmgr_smoke_cheri", "dv_log_smoketest", "dv_log_smoketest_cheri", - "spi_device_smoke", - "spi_device_smoke_cheri", - "spi_host_smoke", - "spi_host_smoke_cheri", - "i2c_host_tx_rx", - "i2c_host_tx_rx_cheri", + "entropy_src_smoke", + "entropy_src_smoke_cheri", "gpio_smoke", "gpio_smoke_cheri", + "i2c_device_tx_rx", + "i2c_device_tx_rx_cheri", + "i2c_host_tx_rx", + "i2c_host_tx_rx_cheri", "mailbox_smoke", "mailbox_smoke_cheri", - "axi_sram_smoke", - "axi_sram_smoke_cheri", + "pwrmgr_smoke", + "pwrmgr_smoke_cheri", "rom_ctrl_smoke", "rom_ctrl_smoke_cheri", "rstmgr_smoke", "rstmgr_smoke_cheri", - "clkmgr_smoke", - "clkmgr_smoke_cheri", - "pwrmgr_smoke", - "pwrmgr_smoke_cheri", - "entropy_src_smoke", - "entropy_src_smoke_cheri", + "rv_dm_smoke", + "rv_dm_smoke_cheri", + "rv_plic_all_irqs_test", + "rv_plic_all_irqs_test_cheri", + "rv_plic_smoke", + "rv_plic_smoke_cheri", + "rv_timer_irq", + "rv_timer_irq_cheri", + "rv_timer_smoke", + "rv_timer_smoke_cheri", + "spi_device_smoke", + "spi_device_smoke_cheri", + "spi_host_smoke", + "spi_host_smoke_cheri", + "tag_ctrl_smoke", + "tag_ctrl_smoke_cheri", + "test_framework_exception_test", + "test_framework_exception_test_cheri", + "test_framework_test", + "test_framework_test_cheri", + "tl_xbar_smoke", + "tl_xbar_smoke_cheri", + "uart_smoke", + "uart_smoke_cheri", + "uart_tx_rx", + "uart_tx_rx_cheri" ] } { - name: uart + name: axi_sram tests: [ - "uart_smoke", - "uart_smoke_cheri" + "axi_sram_smoke", + "axi_sram_smoke_cheri", + "axi_sram_tag_test", + "axi_sram_tag_test_cheri" ] } { - name: rv_plic + name: axi_xbar tests: [ - "rv_plic_smoke", - "rv_plic_smoke_cheri" + "axi_xbar_smoke", + "axi_xbar_smoke_cheri" ] } { - name: rv_timer + name: clkmgr tests: [ - "rv_timer_smoke", - "rv_timer_smoke_cheri", - "rv_timer_irq", - "rv_timer_irq_cheri" + "clkmgr_smoke", + "clkmgr_smoke_cheri" ] } { - name: test_framework + name: entropy_src tests: [ - "test_framework_test", - "test_framework_test_cheri", - "test_framework_exception_test", - "test_framework_exception_test_cheri", - "dv_log_smoketest", - "dv_log_smoketest_cheri" + "entropy_src_smoke", + "entropy_src_smoke_cheri" ] } { - name: spi_device + name: gpio tests: [ - "spi_device_smoke", - "spi_device_smoke_cheri" + "gpio_smoke", + "gpio_smoke_cheri" ] } { name: i2c tests: [ + "i2c_device_tx_rx", + "i2c_device_tx_rx_cheri", "i2c_host_tx_rx", "i2c_host_tx_rx_cheri", - "i2c_device_tx_rx" ] } { - name: gpio + name: kmac tests: [ - "gpio_smoke", - "gpio_smoke_cheri" + "kmac_rom_app_test", + ] + } + { + name: mailbox + tests: [ + "mailbox_ext_tx_rx_test", + "mailbox_ext_tx_rx_test_cheri", + "mailbox_smoke", + "mailbox_smoke_cheri" + ] + } + { + name: pwrmgr + tests: [ + "pwrmgr_lowpower_quiescent_test", + "pwrmgr_lowpower_quiescent_test_cheri", + "pwrmgr_smoke", + "pwrmgr_smoke_cheri", + "pwrmgr_wakeup_test", + "pwrmgr_wakeup_test_cheri" ] } { @@ -476,49 +732,92 @@ ] } { - name: clkmgr + name: rv_dm tests: [ - "clkmgr_smoke", - "clkmgr_smoke_cheri" + "rv_dm_access_after_wakeup", + "rv_dm_access_after_wakeup_cheri", + "rv_dm_cap_reg_access_test_cheri", + "rv_dm_ndm_reset_req", + "rv_dm_ndm_reset_req_cheri", + "rv_dm_ndm_reset_req_when_cpu_halted", + "rv_dm_ndm_reset_req_when_cpu_halted_cheri", + "rv_dm_sba_access", + "rv_dm_sba_access_cheri", + "rv_dm_smoke", + "rv_dm_smoke_cheri" ] } { - name: pwrmgr + name: rv_plic tests: [ - "pwrmgr_smoke", - "pwrmgr_smoke_cheri" + "rv_plic_all_irqs_test", + "rv_plic_all_irqs_test_cheri", + "rv_plic_priority_test", + "rv_plic_priority_test_cheri", + "rv_plic_smoke", + "rv_plic_smoke_cheri" ] } { - name: rv_dm + name: rv_timer tests: [ - "rv_dm_ndm_reset_req", - "rv_dm_ndm_reset_req_when_cpu_halted", - "rv_dm_access_after_wakeup", - "rv_dm_access_after_escalation_reset" + "rv_timer_irq", + "rv_timer_irq_cheri", + "rv_timer_smoke", + "rv_timer_smoke_cheri" ] } { - name: mailbox + name: spi_device tests: [ - "mailbox_smoke", - "mailbox_smoke_cheri" + "spi_device_smoke", + "spi_device_smoke_cheri", + "spi_device_upload_test", + "spi_device_upload_test_cheri" ] } { - name: axi_sram + name: spi_host tests: [ - "axi_sram_smoke", - "axi_sram_smoke_cheri", - "axi_sram_tag_test", - "axi_sram_tag_test_cheri" + "spi_host_smoke", + "spi_host_smoke_cheri", + "spi_host_tx_rx", + "spi_host_tx_rx_cheri" ] } { - name: entropy_src + name: tag_ctrl tests: [ - "entropy_src_smoke", - "entropy_src_smoke_cheri" + "tag_ctrl_dram_test_cheri", + "tag_ctrl_smoke", + "tag_ctrl_smoke_cheri" + ] + } + { + name: test_framework + tests: [ + "dv_log_smoketest", + "dv_log_smoketest_cheri", + "test_framework_exception_test", + "test_framework_exception_test_cheri", + "test_framework_test", + "test_framework_test_cheri" + ] + } + { + name: tl_xbar + tests: [ + "tl_xbar_smoke", + "tl_xbar_smoke_cheri" + ] + } + { + name: uart + tests: [ + "uart_smoke", + "uart_smoke_cheri", + "uart_tx_rx", + "uart_tx_rx_cheri" ] } ]