diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 1d73f3b..2677f2d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,6 +12,9 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 + with: + # Provenance validates a documented ancestor, not just the checkout. + fetch-depth: 0 - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 with: python-version: "3.13" diff --git a/.gitignore b/.gitignore index 28b9b86..83b39a9 100644 --- a/.gitignore +++ b/.gitignore @@ -19,3 +19,18 @@ formal/stream_alu_mul_pulse_induction/ formal/stream_alu_mul_pulse_cover/ openlane/ reports/ + +# Scratch outputs of the ULX3S build scripts. The scripts archive the copies +# that matter under results/. +fpga/ulx3s/smoke_top.* +fpga/ulx3s/ulx3s_top.* +!fpga/ulx3s/smoke_top.sv +!fpga/ulx3s/ulx3s_top.sv + +# Archived build evidence. The blanket *.log rule above would otherwise drop +# the synthesis and route logs that make an immutable bitstream reviewable. +!results/**/*.log + +# ecppack is silent on success; an empty log is not evidence. +results/**/ecppack*.log +results/.ulx3s-smoke-uart.publish.lock diff --git a/SHA256SUMS b/SHA256SUMS index f89f161..d2a8dac 100644 --- a/SHA256SUMS +++ b/SHA256SUMS @@ -1,5 +1,5 @@ -152ebd1753fdc29f26b782a4062080a67449149438fd5026c166a25029d7d47b ./.github/workflows/ci.yml -c5a00dfb7ec29979b10d186838f02a1efe2b42126cda0c65df658d6b4c7bc543 ./.gitignore +520f032c9983bb98548e3316724b8218ef92730c6e3309309fdf6835597e4559 ./.github/workflows/ci.yml +e01c466509630117b96ee5ddac3ad887ec95a932cfd5b1efcff77fe4f3891133 ./.gitignore cfc7749b96f63bd31c3c42b5c471bf756814053e847c10f3eb003417bc523d30 ./LICENSE ca1b6b510bfeb5dc906aa0862e95d962c2901c246fa10fa72296d1666239d601 ./MANIFEST.md c4e56018f86fd8b6fd1cd2e2cb39370b0501e8f83a1d7aeceab163457f9d60e4 ./Makefile @@ -34,8 +34,9 @@ b81b89574ed84c67b64ae7b56001bf9d03b9d66be2bed7977d8adc715481eafb ./docs/PROTOCO 0d787acfaa683bf07cedea98ba403d51079593b50f84b48ee199a479cc35b099 ./docs/SEMANTICS.md 6ec7c4c80628391da706725be1a2361ae8eb2ee014fb4cde6dae31c53f13e9f0 ./docs/SEMANTIC_DIFFERENCES.md 02e8a5b52b341390f008ff8bc62f5d2d982b23adb8b26cb73ef3b07dddeed807 ./docs/SOURCE_AUDIT.md -1ce879d29924a6c8d1c507c6233879428e25b204c6645493b71c401e8a7fcc49 ./docs/STATUS.md +4908edd6fcd6d559bfef07a60eb703b0382bd2e79f126ea8930fb4122d1df1b3 ./docs/STATUS.md 9c2582c40fbd9a4e2b163abed784f5a6c82b2cb3136c37a4123a0ba6584f6136 ./docs/TAPEOUT.md +e61e74c84bce2ec92ef18520eb134299f9341e63d3ec43cdbe0ef4879d22ba37 ./docs/ULX3S_SMOKE_AND_UART.md a08743f1a3cf4af68683cdaac5b00ca624ac875dbeef9f78614bda7297579df8 ./docs/USE_CASES.md 20aa56b3f69c28c9639e9bd16b8239f0ef511d8fded9340185814b3257e25f01 ./docs/VALIDATION.md c8dbcf0008931bfd0d6a27c00425480de54d322dd27367ae83f54f93e3382b8c ./docs/semantics/reference/README.md @@ -52,21 +53,37 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836 ./formal/gf128 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f ./formal/gf8_mul_formal.sv 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e ./formal/stream_alu_mul_pulse.sby b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1 ./formal/stream_alu_mul_pulse_formal.sv +c463f7e5612c93ece40f4bb2163938757d03903de8eed1dd1b85529ea2d0b632 ./fpga/ulx3s/Makefile +2193c115f54fc49c77280a544b0963bbff3cc5840fb5795fdf44e7dcb44f5781 ./fpga/ulx3s/build_smoke.sh +da9ff87e6546086c402879bb6b0f3c21f7df2712c70ad103872462369e222381 ./fpga/ulx3s/build_uart.sh +8243770de3fb1cb65f8ef0ee345addab105cf7e219d0c3be5cf009743e27f59f ./fpga/ulx3s/smoke.config +e9dc79a86095c3c4f9e9d531746ee51c57d301e6840386670b5837aed72062ae ./fpga/ulx3s/smoke.ys +cd4a528e8502a4761efa123743afd1f6e180681af3349f05c5777ee489a92689 ./fpga/ulx3s/smoke_top.sv +b2226a0db5c80da4de9ab630caf40f42678cb15acd3fa2f4f661f5d101146931 ./fpga/ulx3s/uart_bridge.sv +b51f1a3974e7ae32bcbf9c32716aa9eb7d205e46e158a3f535bac7c04a57f7de ./fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 ./fpga/ulx3s/uart_tx.sv +76513d0e0245b1e212b71ad56fdafeaa0a9654535a665f977bee4ef41a5bbd8f ./fpga/ulx3s/ulx3s_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 ./fpga/ulx3s/ulx3s_v318_smoke.lpf 85af4e1517f0bec1e0d586690d29c93b58ae9d3095c22cb081d184f51f79cd62 ./fpga_harness/BOUNDARY.md -a25abf613168eb6fa3c1d45ccfb26e9c7eadf95f8445616d6030cc038d4b867d ./fpga_harness/BUILD_PLAN.md -1904480b3c114a1edb2f33add69bf493017c206aeb572b307d83f73a8bc8ac6e ./fpga_harness/INVENTORY.md -a97901243c2eb074f5b43eb3b620bf3675cbd2ecd415d9a945dda1acc7499d80 ./fpga_harness/README.md -10365c2a44923b680ff5c8a1069af89508ac94d895d07c618ebca609d9343375 ./fpga_harness/board_detect.py +dad7d78465d3b8f339d22d79c0823e52dc587fba26272b4f6fd7ce6ed1de6201 ./fpga_harness/BUILD_PLAN.md +5afe24acc0e398a66591f66ef62fb63ca300c2f925f9de828547e7e9ea8b302e ./fpga_harness/INVENTORY.md +c58d6e0e447f6da7ffc769899ba021e386d4effdd27a987bdb0ece8235f3ebac ./fpga_harness/README.md +a538a3b5e64df095b867eb23f77953be4ea021a5d755f45f13a7b9a8ed8e7ccb ./fpga_harness/board_detect.py f00b4c8c96b74b20c75ebc0cd3cc042def53f39d9cf1d963435e9b2e8f96e176 ./fpga_harness/boundary_check.py ac042826f976c6e04c668613676b006743f487a463e2cd6a2ca14a5f31571502 ./fpga_harness/fixtures/ulx3s_full_visibility.json 7571676d26daf04b94b9fadbdbc9740568ea92439ae0830f41a7567fdbd002a7 ./fpga_harness/host/__init__.py 9192a6565a1e455bc0a2143bdf293bc201505e6a964a1ac38f2025874713bf36 ./fpga_harness/host/mincore_uart.py 93dbd041aaec9b476b5b1da6b9fced4740967a779b7bd130544f4d93777c09bd ./fpga_harness/rtl/lean_silicon_lsc1_pins.sv +608b33eb1cc3f5d63216e7e3074b0635e5d00ba4914d45bba0f0759f011ead12 ./fpga_harness/test_artefact_provenance.py +8a9679c14d7201984cf164741dc7c96599e8ce73b03f176e223bff593250cb95 ./fpga_harness/test_atomic_publish.py 9a4439844c2bc2f486a470a3cbbad271f7d1df5bef9da103a2fd80e3a9d49071 ./fpga_harness/test_board_detect.py 523c4171885c2a1621be25812b0ac283b7ce6272a19b2a60a5b7b4240ce9bdef ./fpga_harness/test_boundary_check.py +00b12cbb73f0054731dd8ed1f7d4d5646fbcffec4699cca8b54d340607edc3e4 ./fpga_harness/test_portable_build_support.py +3f87f766a0b5dcde66bcce9b25b420c0993a1c789caf045f6c91472f033dbe16 ./fpga_harness/test_ulx3s_uart.py ee455920032996e22976f2ddba66233deb1d6c7a0c2052f07a5522a08650165b ./fpga_harness/tests/__init__.py 02666faf1c09b2e31f7b185707f9059b4e425e6f80c04517534583b41d5360a2 ./fpga_harness/tests/host_uart/__init__.py 5f9dc24a932d06558761458da8c5926605f9ca37ae662e342dae0aef92823479 ./fpga_harness/tests/host_uart/test_mincore_uart.py +20b18779647bb635239ad75a2ee36c9e83b3014ff0fd8fd13a9e7eb0aa3754d4 ./fpga_harness/ulx3s_uart.py 1e70f22fc5e73c872a0a2c1b764d4c10ec4df9150b47c9d5a19b9a6183af593b ./host/README.md a8294c47be51b34fd3d8f80499618218838d3dece1e3d6b06f8e704ee02ca25f ./host/__init__.py 8fb848653468cf64ecf26e1d7acf598fe30027630ebe1941ec8424ee2f0a6079 ./host/errors.py @@ -95,7 +112,7 @@ d1f2dfa6bf564b9cf248838630eb92efd55f03e9ab8bf5e7dfec3d318b9f0f29 ./lean/lakefil 8e3538e0ab5f81a3ee04927d8838c8c674e0e112838b4b3ce87ec218143276af ./lean/lean-toolchain d59a11f361717058c708574a6f41d9be99da29cfcc3b0c033045ce6f0e57a5d5 ./planning/OWNERSHIP.md a19467b08293daf14a67ccd8f0efbcddfeb3854c38525acd7fcfd98f01552587 ./planning/milestones.yaml -01e08410080741c1f164e3b7459ea15db5966cef6629bfeb2691175f269efd00 ./requirements.txt +1625e15cb9fb79c40afc1ab30e2a3483f5158253b0cc34f0cf84970ebcb9c2e3 ./requirements.txt 73c8c4939d05b6fd2367c8fc992e8386ee1b505499abfd1050b8286022589f9c ./results/fpga-harness-inventory-20260725/README.md 13c80bbee4874817634c3edcef6a6a687fd4e6d1d5412c026fe9b314388eeb7c ./results/fpga-harness-inventory-20260725/fpga-boundary.log 9a271f2a916b0b6ee6cecb2426f0b3206ef074578be55d9bc94f6f3fe3ab86aa ./results/fpga-harness-inventory-20260725/fpga-boundary.status @@ -253,6 +270,22 @@ c05bcfb6cfbeaa2f72eb031a986a37e6094ec430022d6cce911cf4fcedfb101a ./results/seri 42f3d4668a80ab3bf2a16915803d5a212bb299ca8800fa24dfc0f8baaa88c509 ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.log ceceba3b9bc693c4b5a87f799e91ee36f93c483dd32d6e32514eb2a3e02779ad ./results/serial-mul-byte-order-20260725/sby-stream-alu-mul-pulse-induction.status 228b1eb2253fe285abf3f2d6cf6a7748661a11367433e17a8cef8832ea6068e4 ./results/serial-mul-byte-order-20260725/toolchain.txt +0d617e2e80e8749ea5f1b0a48f2da7ddac62dcb5f8def09126d60971f26dbf36 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS +ecd004f3008420bdf304a9d8f1084202847f65836bafed2aef69b858db180628 ./results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt +7b45b067f30eb0a477f2eea894f79b0694ee3dcfb78752c935a2aa13c2a53d51 ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt +dbda64dd3a2c4985c6d2a98123daac73461e2cb4d1ffb18da445920d5f2fe19b ./results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt +353825c15c00249b61be316b86c75c664a9ee2142a99a14f58a5fe7190d31830 ./results/ulx3s-smoke-uart-20260725/nextpnr.log +f76f35d01b2f93608843c292ad056158f5be23ca61b5e8d61898d4732f75cb85 ./results/ulx3s-smoke-uart-20260725/nextpnr_uart.log +8243770de3fb1cb65f8ef0ee345addab105cf7e219d0c3be5cf009743e27f59f ./results/ulx3s-smoke-uart-20260725/smoke.config +0a2dcd734f194819b6483b6d5a7e394677eb30634760d46a62d4f5542cdec944 ./results/ulx3s-smoke-uart-20260725/smoke.svf +e81003f252d7b36ca38a0e95c2be813ea383dd919c06d0d53c6b56326cbd3cc6 ./results/ulx3s-smoke-uart-20260725/timing.txt +435e10f7f36b9eec93cc0f88c660c2bcb570e279465ef11455fa251a65df7fcb ./results/ulx3s-smoke-uart-20260725/timing_uart.txt +5be356b89eb518e7af532be06af0368c8831554db03db7787192310c99a1781e ./results/ulx3s-smoke-uart-20260725/tool_versions.txt +6b761d5b6c0e60e130a7bc81cbb9f491ae329a9175376bbdfd6b2f6b624da4b6 ./results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt +eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51 ./results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit +96eb9eda7421bac902eacaeced21eee0db9a80b8f2f2effdb52b515d68e0b2e3 ./results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit +e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d ./results/ulx3s-smoke-uart-20260725/yosys.log +7d50c170f623ccc6911a48dd18455bc1011a2be335a9997c6d85355d0c72e63d ./results/ulx3s-smoke-uart-20260725/yosys_uart.log 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c ./sim/__init__.py 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c ./sim/cycle_model.py 3ebec652b76c20903fde598d748dbaff596cbc3f962f80ca23f30b31e1327da5 ./sim/lsc1_transaction.py @@ -260,6 +293,7 @@ ceceba3b9bc693c4b5a87f799e91ee36f93c483dd32d6e32514eb2a3e02779ad ./results/seri dee5dc820b96f24d4dbd752b17aaad3c8e025d519c043dfd1ab7c46be5600245 ./sim/packet_executor_model.py 659496fd9f21edafb7c4c12500d9b623bd0ea063808dc9494053ad923102dc31 ./sim/protocol_contract.py 33a0956687b75cb08d19e58a7da8fc4acf622e63795f1220f57a38bc6d2c4117 ./sim/scalar_step_oracle.py +d14a3e8aed08ece9ce5d9ac4ddc2d29bf218dcb4626592a11ff63eb36fe454dc ./sim/test_atomic_publish.py a2fda9c21da5f3301de411060ffbb644c08c4c5e4c103e036b3834e2922ce10a ./sim/test_cycle_model.py e6b030e8b15a0a73764faa3eedfeb937c6d8e8080bb17bf495cae3085c8dce26 ./sim/test_host_runtime.py f1ab500117ae9d7a20a9258a32dbc7271b4d0ec5f57d3fc058ff426ba2289a40 ./sim/test_lsc1_protocol_doc.py @@ -274,11 +308,13 @@ f3e038032b2f1c76b176651dd79b266976091f1215b7e617c194888e387ab5e5 ./src/leanvm_b bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b ./src/leanvm_b_stream_alu.sv e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c ./src/tt_um_leanvm_b_mincore.sv a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331 ./src/user_config.tcl -a021052d2cc38de0bbd8994680d8a647c7e55e3a3f3c77f5098d0dce9a29e843 ./test/Makefile +a66afe03d6bc6e5993a13206a70236f13b185765e9798dd6033e7279123d556c ./test/Makefile fcfcaf4f52e98837efe8a505ae8271beb1a4659504672cd1617aec1f93506f27 ./test/packet_frontend/Makefile 799f514bf69c23fdef237d0d9ff6f64381a55c4228532c6e60a0e07e6e008de8 ./test/packet_frontend/tb_lsc1_packet_frontend.sv d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077 ./test/tb_m2_scalar_controller.sv b78b938f396ae20d1fdccde99281430778a879808e60a35788b6fe044151329c ./test/tb_stream_alu.sv +1cdfef46a813dd43f5700b5e3ed7ec0bfb07e07403c82f8ac8fa4fb4dfbd0d55 ./test/tb_uart_bridge.sv +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a ./tools/atomic_publish.py 008f814b114282389ae48ff82e4412fe455cbe8c377cf71e534862d490d3cb79 ./tools/design_space.csv 54dca27c0adde9d13728952216a7cb7027cabacb4742e5bb26f063613c05c557 ./tools/design_space.md 63693e361330234c6ba3cbfff282f808cc9ffda85cb074ec1de1d7d1fb3954b5 ./tools/design_space.py @@ -289,6 +325,8 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919 ./tools/frozen 16a04bf83da566c67f35f43d46db71c464b9f08e60952cae9b51419b33ec65fe ./tools/interface_consistency.py 87bf0131d197add11cab19ba34e9278a16dddcc066e254ca77b3c28d46b9da4b ./tools/lean_compiler_export.py 13cda9f3b47fda14a1ea23b3e210212eacd7250ea15ffd1e1ac638ea0d5bff3a ./tools/m2_rtl_differential.py +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 ./tools/portable_build_support.py af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0 ./tools/repo_consistency.py 8b848ef50be2f01f34cac16e44469a18e3b4c087a5d6434cae71d4919a446c6b ./tools/rtl_state_count.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db ./tools/source_provenance.py 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d ./tools/sv_smoke_check.py diff --git a/docs/STATUS.md b/docs/STATUS.md index 266e9b6..4becbf0 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -11,7 +11,7 @@ | lean_compiler integration | artifact exported from the frozen compiler; `hints`/`main_frame`/`witness`/`trace` are `pub(crate)` upstream | `tools/lean_compiler_export.py`, `docs/HOST_RUNTIME.md` section 4 | | Host vs frozen Rust comparison | final memory only, for the 12 cells the fixture run touched; `cycles` and every per-step field explicitly not compared | `tools/host_upstream_comparison.py`, `docs/HOST_RUNTIME.md` section 5 | | Full scalar semantics | not implemented | planned graph | -| ULX3S harness bitstream | not implemented | pin contract only | +| ULX3S harness bitstreams | source-built, archived; not hardware-validated | `docs/ULX3S_SMOKE_AND_UART.md`, `results/ulx3s-smoke-uart-20260725/` | | Tiny Tapeout PPA / official zkDSL validation | not run for LSC-1 | planned graph | | Full-controller SV-to-frozen-ISA theorem | not implemented | `docs/PROOF_BOUNDARIES.md` | | RTL-to-netlist equivalence | not implemented | `docs/PROOF_BOUNDARIES.md` | diff --git a/docs/ULX3S_SMOKE_AND_UART.md b/docs/ULX3S_SMOKE_AND_UART.md new file mode 100644 index 0000000..ac75a2a --- /dev/null +++ b/docs/ULX3S_SMOKE_AND_UART.md @@ -0,0 +1,245 @@ +# ULX3S v3.1.8 Smoke and UART Harness (Sprint Deliverable) + +**Status**: Reviewable artefacts only. Never merged. Never programmed to hardware. + +## Worktree and provenance +- Branch base: `03926bbbbdc907d74214e4004985d36055d93a76` (`origin/main`). This is + the pre-feature revision the branch was cut from. It contains none of the + `fpga/ulx3s` design or build files, so it cannot build or identify the + artefacts and must not be read as their source. +- Artefact source revision: `a11c521a0a09168ff91a0ffcf0aa3fd5787f8271` + (clean tree at the point provenance was recorded). Both source manifests record + this full object ID, including every RTL, constraint, recipe and build-support + input. The ID is historical context only: a squash may legitimately make this + feature-branch object unreachable. Verification is deliberately independent of + it: the committed source manifests content-address every input, and CI copies + those inputs into a tree with no `.git` directory before checking every digest. + The bitstreams and supporting files are archived under results/ with those + self-contained manifests, so the evidence remains auditable after a squash. +- Design sources (RTL and LPF) unchanged in netlist effect since an earlier + published ancestor; the manifests at the artefact source revision capture the + complete build-input set (RTL + LPF + recipes + support) used for these + artefacts. The RTL and LPF alone have been unchanged in netlist effect since + `01e7046`; later process-group support changes are captured in the manifests + at the artefact source revision. +- Branch: `fpga/ulx3s-smoke-uart-mincore` +- Ownership: PR #13 owns host runtime files; PR #15 owns `board_detect/tests/global` and SHA256SUMS. Those paths untouched. + +## Board facts (confirmed) +- PCB: v3.1.8 +- FPGA: LFE5U-85F, IDCODE 0x41113043 +- Clock: 25 MHz onboard at G2 +- LED0: B2 (active low) +- US1 FT231X UART: + - FPGA RX (host TX): M1 (ftdi_txd) + - FPGA TX (host RX): L4 (ftdi_rxd) +- SDRAM: unused +- macOS cu/tty pair for US1 + +**LPF note**: `fpga/ulx3s/ulx3s_v318_smoke.lpf` is a **pin-subset hypothesis** derived from ulx3s-misc v316 (v3.1.6/3.1.7). v3.1.8 applicability is unconfirmed beyond G2/B2/M1/L4 stability across v3.x. No full board LPF reproduced. + +## P0 smoke (counter/LED heartbeat) +- RTL: [fpga/ulx3s/smoke_top.sv](../fpga/ulx3s/smoke_top.sv) +- Constraints: [fpga/ulx3s/ulx3s_v318_smoke.lpf](../fpga/ulx3s/ulx3s_v318_smoke.lpf) +- Build script: [fpga/ulx3s/build_smoke.sh](../fpga/ulx3s/build_smoke.sh) + +### Toolchain (pinned OSS CAD Suite 2026-07-25) +Reproduced verbatim in `results/ulx3s-smoke-uart-20260725/tool_versions.txt`: +``` +Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.10-100-gfb95bb8e) +Project Trellis ecppack Version 1.4-79-g56bb170 +``` + +### Exact commands executed (no --timing-allow-fail) +```sh +make -C fpga/ulx3s smoke # runs fpga/ulx3s/build_smoke.sh +``` +The script resolves the repository root from its own location, so it may be run +from any working directory. It archives the bitstream, config and SVF into +`results/ulx3s-smoke-uart-20260725/` under the names the manifest lists, writes +`SHA256SUMS` there, and then re-verifies it with `sha256sum -c` before exiting. + +### Post-route timing (captured) +The LPF carries `FREQUENCY PORT "clk" 25.000000 MHz`. Without it nextpnr falls +back to a 12 MHz default and a passing report says nothing about the real board +clock. +``` +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 291.97 MHz (PASS at 25.00 MHz) +``` + +### Bitstream artefacts +- `results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit` +- SHA256: `96eb9eda7421bac902eacaeced21eee0db9a80b8f2f2effdb52b515d68e0b2e3` + +## P1 UART + bridge (1 Mbaud) +- UART RX/TX: [fpga/ulx3s/uart_rx.sv](../fpga/ulx3s/uart_rx.sv), [uart_tx.sv](../fpga/ulx3s/uart_tx.sv) + - 1 Mbaud at 25 MHz (DIV=25) + - 2-flop synchroniser on RX + - Framing error detection; byte dropped on error +- Bridge: [fpga/ulx3s/uart_bridge.sv](../fpga/ulx3s/uart_bridge.sv) + - Instantiates **exact** `lean_silicon_lsc1` (MinCore seed, not v1 packet) + - One-deep skid buffer in each direction. Each buffer's ready signal deasserts + on the same handshake that fills it, so no byte is presented to a side that + has not signalled room for it and none is replaced before the far side took it. + - `RX_VALID` is held until the core completes the handshake, rather than pulsed + against a ready sampled a cycle earlier. + - `TX_READY` is the transmit buffer's empty flag, not a mirror of the + serialiser's ready one cycle late. + - POR reset: a zero-initialised shift register, so `rst_n` is genuinely held + low for 8 edges before release. A synchroniser that only ever shifts in ones + never asserts reset at all and leaves the whole design at `x`. + - Sticky `rx_overrun` observability probe: set if a byte arrives while the + receive buffer is full and not draining. It drives no logic; the testbench + asserts it stays clear. + - Framing error or 0x7f byte produces ABORT pulse +- Top: [fpga/ulx3s/ulx3s_top.sv](../fpga/ulx3s/ulx3s_top.sv) (USE_SMOKE=0 selects bridge) +- Build: [fpga/ulx3s/build_uart.sh](../fpga/ulx3s/build_uart.sh) + +### Bridge post-route (same flow) +Built with `make -C fpga/ulx3s uart`. +``` +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 154.37 MHz (PASS at 25.00 MHz) +``` +Device utilisation confirms the core is really in the image, not optimised away: +703 TRELLIS_COMB and 402 TRELLIS_FF against 34/25 for the bare smoke design. +Only 4 TRELLIS_IO are used (`clk`, `led`, `uart_rx`, `uart_tx`), so the 8-bit +ASIC boundary is not widened out to pins. +- Bitstream: `results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit` +- SHA256: `eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51` +- Byte-identical across two independent runs of the build script. + +## P1 Python driver (new harness-owned path) +- [fpga_harness/ulx3s_uart.py](../fpga_harness/ulx3s_uart.py) +- **Explicit serial path only**. No enumeration. No persistence. No auto-detect. +- Commands: `--tx set|xor|mul|status|clear --port /dev/... --payload ` +- Independent expected values for SET, XOR **and MUL**. The MUL expectation is + computed locally by both oracles in `sim/model.py` (schoolbook carry-less + multiply plus long reduction, and the LSB-first bit-serial recurrence) and + cross-checked against each other. The process exit status depends on the + comparison, so a complete but incorrect 16-byte product exits 1 rather than 0. +- STATUS is checked against the fixed `01 01 0f 08` signature the RTL emits, so + four garbage bytes exit 1. This matters because `status` is the default `--tx`. +- Stale-byte drain on open and between transactions. +- Timeout and clear/status support. + +### Known transport limitation: `0x7f` is not carried transparently + +`uart_bridge.sv` raises its abort pulse on **any** received `0x7f`, not only on +one in command position, so a `0x7f` inside an operand tears the transaction +down mid-flight. Reproduced in simulation: a SET128 whose payload byte 5 is +`0x7f` returns 15 bytes, with `0xe0` from byte 5 onward instead of the echo. +A 128-bit operand is arbitrary data, so an unlucky vector hits this — roughly +6% of random SET payloads and 12% of random XOR/MUL operand pairs. + +Until the bridge framing distinguishes payload bytes from command bytes, the +driver refuses such an operand and exits **2** (tooling limit) rather than 1 +(board answered wrong), so it cannot be misread as a silicon fault. This is an +open design question on the bridge, not a property of `lean_silicon_lsc1`: the +ASIC takes ABORT on `uio_in[6]`, a pin, and has no in-band abort byte. + +Example (never run on hardware without review): +```sh +python3 -m pip install -r requirements.txt +python3 -m fpga_harness.ulx3s_uart --port /dev/ttyUSB0 --tx status +python3 -m fpga_harness.ulx3s_uart --port /dev/ttyUSB0 --tx set --payload 00000000000000000000000000000000 +``` + +## P2 Tests +- Boundary: `make fpga-boundary` (and direct `python3 fpga_harness/boundary_check.py`) → OK +- Harness unit tests: `make fpga-harness` → 139 tests OK +- Sim: `make python` → 163 tests OK +- Icarus benches: `make sim` builds and runs both `test/tb_stream_alu.sv` and + `test/tb_uart_bridge.sv`. The bridge bench is wired into the target rather + than run by hand, so a regression in it fails the suite. + +`tb_uart_bridge` contains a real 1 Mbaud 8N1 receiver, not a liveness window. +It fails on a response byte that is never serialised, on a stop bit that is not +high, on a final data bit not held for a full baud interval, on any byte that +differs from an independently computed expectation, on an unexpected extra byte, +and on `rx_overrun`. Covered transactions: STATUS, SET with an all-zero payload, +SET with a mixed payload, XOR, MUL against the `sim/model.py` vector, unknown +opcode → `0xe0`, and abort-then-recover. + +Mutation testing was used to show the bench and the harness tests actually +discriminate, rather than passing because the code happens to be correct: + +| Mutation | Reintroduced defect | Result | +| --- | --- | --- | +| M1 | `uart_tx` releases `tx_ready` at `bit_cnt == 8` | caught — `byte 0 is 81, expected 01` | +| M4 | POR shift register that only shifts in ones | caught | +| MA | Original `uart_bridge.sv` ready/valid logic verbatim | caught — STATUS receives 2 of 4 bytes, SET 8 of 16 | +| MB | `--tx mul` returns 0 without comparing | caught by 4 harness tests | + +Run order used: +```sh +make check # includes fpga-boundary, fpga-harness, checksum-check +make sim # both Icarus benches +``` + +## Programming (SRAM-only, review gate) +**Never execute before independent review.** + +```sh +# SRAM load only (volatile). Power cycle to recover. +openFPGALoader -b ulx3s results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit +# or for bridge: +openFPGALoader -b ulx3s results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit +``` + +**Explicit prohibition**: Do not pass `-f` (flash). This design is SRAM-only smoke. Flash would persist a partial harness across power cycles and violates the "review before any hardware" rule. + +Power-cycle recovery: remove power or press reset; SRAM contents are lost. + +## What this is not +- Not a CPU/ISA validation. +- Not a datapath validation on silicon. +- Not a claim that bytes crossed a physical ULX3S. +- The artefacts prove: reproducible OSS flow from the exact source recorded under "Worktree and provenance" above, exact `lean_silicon_lsc1` pin contract instantiated, post-route timing closed against an explicit 25 MHz constraint, and clean tests. + +## Supported transaction sequence (MinCore protocol) +- SET128 (0x03): 1+16 bytes in → 16 bytes echo +- XOR128 (0x01): 1+32 bytes (A,B interleaved) → 16 bytes +- MUL128 (0x02): 1+32 bytes (A then B) → 16 bytes +- STATUS (0x7e): 1 byte → 4 status bytes +- CLEAR (0x7d): 1 byte, no response, clears sticky fault +- ABORT via uio_in[6] (from framing error or 0x7f byte) + +All bytes traverse ui_in/uo_out/uio_* ready/valid. No wide bypass. + +## Blockers / limits +- No physical ULX3S attached in sprint environment. +- No Verilator full bridge test (Icarus only; Verilator would require additional wrapper). +- Bridge driver lacks host-side flow control backpressure beyond TX_READY gating. +- LPF is hypothesis only for v3.1.8; full pin list and bank voltages unverified here. +- **0x7f cannot appear as a payload byte.** The bridge treats it as an abort at + the byte layer, before any command framing, so a SET/XOR/MUL operand + containing 0x7f aborts the transaction instead of being delivered. This is the + documented ABORT contract, not a regression; escaping or framing the payload + would change the wire protocol and is deliberately out of scope for this PR. +- The bridge is one byte deep in each direction. That is sufficient here because + the host is slower than the core, but it is not a general flow-control layer. + +## Artefact manifest (local) +Every file listed below is present in the committed results directory. Verify with +`cd results/ulx3s-smoke-uart-20260725 && sha256sum -c SHA256SUMS && sha256sum -c SHA256SUMS_bridge.txt` on Linux, or +`cd results/ulx3s-smoke-uart-20260725 && shasum -a 256 -c SHA256SUMS && shasum -a 256 -c SHA256SUMS_bridge.txt` on stock macOS. +``` +results/ulx3s-smoke-uart-20260725/ + SHA256SUMS # ulx3s_smoke.bit, smoke.config, smoke.svf + SHA256SUMS_bridge.txt # ulx3s_bridge.bit + ulx3s_smoke.bit # 96eb9eda... + ulx3s_bridge.bit # eacee77b... + smoke.config + smoke.svf + tool_versions.txt tool_versions_uart.txt + yosys.log yosys_uart.log + nextpnr.log nextpnr_uart.log + timing.txt timing_uart.txt +``` +`ecppack` emits nothing on success, so its log is not archived; an empty file +would not distinguish a silent run from a run that never happened. +The repository `.gitignore` excludes `*.log` globally; this directory is +exempted so the synthesis and route evidence is actually reviewable. + +All deliverables stop at the verified boundary. No fabricated execution logs. diff --git a/fpga/ulx3s/Makefile b/fpga/ulx3s/Makefile new file mode 100644 index 0000000..b7aeba1 --- /dev/null +++ b/fpga/ulx3s/Makefile @@ -0,0 +1,24 @@ +# Local FPGA make targets for the sprint worktree +# These are intentionally NOT wired into the repo root Makefile. +# Run from this directory after sourcing an OSS CAD Suite env. + +SHELL := /bin/sh +PYTHON ?= python3 +ROOT := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/../..) + +.PHONY: smoke uart sim clean + +smoke: + ./build_smoke.sh + +uart: + ./build_uart.sh + +sim: + $(MAKE) -C $(ROOT)/test sim + cd $(ROOT) && $(PYTHON) -m unittest discover -s fpga_harness -v + +clean: + rm -f smoke_top.json smoke_top.config smoke_top.bit smoke_top.svf + rm -f ulx3s_top.json ulx3s_top.config ulx3s_top.bit ulx3s_top.svf + rm -f ecppack.log ecppack_uart.log diff --git a/fpga/ulx3s/build_smoke.sh b/fpga/ulx3s/build_smoke.sh new file mode 100755 index 0000000..708bf9f --- /dev/null +++ b/fpga/ulx3s/build_smoke.sh @@ -0,0 +1,112 @@ +#!/bin/sh +# Reproducible ULX3S v3.1.8 smoke build. +# Requires: yosys, nextpnr-ecp5, ecppack from OSS CAD Suite (no -f ever). +set -eu + +# Resolve the repository root from this script's location. The build products +# are archived into the committed results directory, so a wrong number of ".." +# silently scatters evidence outside the repository instead of failing. +HERE=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) +ROOT=$(CDPATH= cd -- "$HERE/../.." && pwd) +cd "$HERE" + +TOP=smoke_top +LPF=ulx3s_v318_smoke.lpf +OUTDIR="$ROOT/results/ulx3s-smoke-uart-20260725" +SUPPORT=../../tools/portable_build_support.py +mkdir -p "$OUTDIR" +# Both FPGA flows publish into OUTDIR. Keep the lock outside that directory so +# its inode remains stable while OUTDIR itself is atomically exchanged. +LOCK="$ROOT/results/.ulx3s-smoke-uart.publish.lock" +if [ "${ULX3S_BUILD_LOCKED:-}" != 1 ]; then + exec python3 "$SUPPORT" lock "$LOCK" -- "$0" "$@" +fi +STAGE=$(mktemp -d "$(dirname "$OUTDIR")/.smoke-build.XXXXXX") +trap 'rm -rf "$STAGE"' EXIT HUP INT TERM +cp -a "$OUTDIR/." "$STAGE/" + +# Names the artifacts are archived and checksummed under. They must match the +# files committed under results/, otherwise `sha256sum -c` names a file that +# does not exist and the manifest cannot be verified. +BIT_NAME=ulx3s_smoke.bit +CFG_NAME=smoke.config +SVF_NAME=smoke.svf + +OSS_CAD_BIN=${OSS_CAD_BIN:-/root/oss/bin} +if [ -d "$OSS_CAD_BIN" ]; then + PATH="$OSS_CAD_BIN:$PATH" + export PATH +fi + +{ + echo "=== TOOL VERSIONS ===" + yosys -V + nextpnr-ecp5 --version + ecppack --version + echo "date: $(date -u +%Y-%m-%dT%H:%M:%SZ)" +} > "$STAGE/tool_versions.txt" 2>&1 +cat "$STAGE/tool_versions.txt" + +# Record which revision these exact inputs came from, so the archive identifies +# its own source instead of relying on a hand-maintained note. The recipe is an +# input as much as the RTL is: changing a yosys or nextpnr flag here changes the +# bitstream, so a manifest that digests only the RTL and $LPF would still report +# a match for an artifact HEAD cannot reproduce. +RECIPE=$(basename -- "$0") +python3 "$ROOT/tools/source_provenance.py" "$STAGE/SOURCE_MANIFEST.txt" \ + "${TOP}.sv" "$LPF" "$RECIPE" "$SUPPORT" "$ROOT/tools/atomic_publish.py" \ + "$ROOT/tools/source_provenance.py" + +echo "=== SYNTH ===" +yosys -p "read_verilog -sv ${TOP}.sv; hierarchy -check -top ${TOP}; proc; check; synth_ecp5 -top ${TOP}; write_json ${TOP}.json" \ + > "$STAGE/yosys.log" 2>&1 || { + status=$? + cat "$STAGE/yosys.log" + exit "$status" +} +cat "$STAGE/yosys.log" + +echo "=== PLACE+ROUTE (25 MHz, no --timing-allow-fail) ===" +nextpnr-ecp5 --85k --package CABGA381 --json ${TOP}.json --lpf ${LPF} --textcfg ${TOP}.config \ + > "$STAGE/nextpnr.log" 2>&1 || { + status=$? + cat "$STAGE/nextpnr.log" + exit "$status" +} +cat "$STAGE/nextpnr.log" + +echo "=== PACK ===" +ecppack --svf ${TOP}.svf ${TOP}.config ${TOP}.bit > "$STAGE/ecppack.log" 2>&1 || { + status=$? + cat "$STAGE/ecppack.log" + exit "$status" +} +cat "$STAGE/ecppack.log" + +cp "${TOP}.bit" "$STAGE/$BIT_NAME" +cp "${TOP}.config" "$STAGE/$CFG_NAME" +cp "${TOP}.svf" "$STAGE/$SVF_NAME" + +# Digest the archived copies from inside OUTDIR so the manifest holds bare +# file names that resolve when checked from that directory. +python3 "$SUPPORT" manifest "$STAGE" SHA256SUMS \ + "$BIT_NAME" "$CFG_NAME" "$SVF_NAME" +python3 "$SUPPORT" check "$STAGE" SHA256SUMS + +# Capture timing line for report +grep -E 'Max frequency|Slack' "$STAGE/nextpnr.log" | tail -5 > "$STAGE/timing.txt" || true + +# The stage is a complete archive snapshot. Exchange the whole directory in +# one same-filesystem operation so failure or interruption cannot expose a +# mixture of old artifacts and new checksums. +# Revalidate after every tool has consumed the working-tree paths. If an input +# changed during synthesis or routing, the pre-build manifest no longer +# describes the produced artifact and publication must stop. +python3 "$ROOT/tools/source_provenance.py" --check "$STAGE/SOURCE_MANIFEST.txt" +python3 "$ROOT/tools/atomic_publish.py" "$STAGE" "$OUTDIR" +cat "$OUTDIR/timing.txt" + +echo "=== BUILD COMPLETE ===" +ls -l "$OUTDIR/$BIT_NAME" +echo "bitstream: $OUTDIR/$BIT_NAME" +echo "sha256: $(python3 "$SUPPORT" digest "$OUTDIR/$BIT_NAME")" diff --git a/fpga/ulx3s/build_uart.sh b/fpga/ulx3s/build_uart.sh new file mode 100755 index 0000000..07d3bf2 --- /dev/null +++ b/fpga/ulx3s/build_uart.sh @@ -0,0 +1,115 @@ +#!/bin/sh +# Build the UART bridge + lean_silicon_lsc1 for ULX3S v3.1.8. +# SRAM-only. Never use -f. +set -eu + +# Resolve the repository root from this script's location. The RTL sources live +# under $ROOT/asic_core; a wrong number of ".." makes yosys read from outside +# the repository (or fail), and sends evidence outside the committed results +# directory. +HERE=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) +ROOT=$(CDPATH= cd -- "$HERE/../.." && pwd) +cd "$HERE" + +TOP=ulx3s_top +LPF=ulx3s_v318_smoke.lpf +OUTDIR="$ROOT/results/ulx3s-smoke-uart-20260725" +SUPPORT=../../tools/portable_build_support.py +mkdir -p "$OUTDIR" +LOCK="$ROOT/results/.ulx3s-smoke-uart.publish.lock" +if [ "${ULX3S_BUILD_LOCKED:-}" != 1 ]; then + exec python3 "$SUPPORT" lock "$LOCK" -- "$0" "$@" +fi +STAGE=$(mktemp -d "$(dirname "$OUTDIR")/.uart-build.XXXXXX") +trap 'rm -rf "$STAGE"' EXIT HUP INT TERM +cp -a "$OUTDIR/." "$STAGE/" + +# Name the artifact is archived and checksummed under; must match the file +# committed under results/. +BIT_NAME=ulx3s_bridge.bit + +OSS_CAD_BIN=${OSS_CAD_BIN:-/root/oss/bin} +if [ -d "$OSS_CAD_BIN" ]; then + PATH="$OSS_CAD_BIN:$PATH" + export PATH +fi + +{ + echo "=== TOOL VERSIONS (UART) ===" + yosys -V + nextpnr-ecp5 --version + ecppack --version + echo "date: $(date -u +%Y-%m-%dT%H:%M:%SZ)" +} > "$STAGE/tool_versions_uart.txt" 2>&1 +cat "$STAGE/tool_versions_uart.txt" + +# Collect sources: bridge + uart + exact ASIC top + MinCore + multiplier. +# Relative to this directory, which the cd above guarantees, so the paths that +# land in the archived yosys log are repository-relative and identical on any +# machine. The repository root is two levels up, not three. +SOURCES="ulx3s_top.sv uart_bridge.sv uart_rx.sv uart_tx.sv \ + ../../asic_core/rtl/lean_silicon_lsc1.sv \ + ../../asic_core/rtl/leanvm_b_stream_alu.sv \ + ../../asic_core/rtl/gf128_mul_bitstream.sv \ + ../../asic_core/rtl/gf2n_mul_bitstream.sv" + +for src in $SOURCES; do + [ -f "$src" ] || { echo "missing source: $src" >&2; exit 1; } +done + +# Record which revision these exact inputs came from, so the archive identifies +# its own source instead of relying on a hand-maintained note. The recipe is an +# input as much as the RTL is: changing a yosys or nextpnr flag here changes the +# bitstream, so a manifest that digests only $SOURCES and $LPF would still +# report a match for an artifact HEAD cannot reproduce. +RECIPE=$(basename -- "$0") +python3 "$ROOT/tools/source_provenance.py" "$STAGE/SOURCE_MANIFEST_uart.txt" \ + $SOURCES "$LPF" "$RECIPE" "$SUPPORT" "$ROOT/tools/atomic_publish.py" \ + "$ROOT/tools/source_provenance.py" + +echo "=== SYNTH (full bridge + MinCore) ===" +yosys -p " +read_verilog -sv $SOURCES; +hierarchy -check -top ${TOP}; +proc; check; +synth_ecp5 -top ${TOP}; +write_json ${TOP}.json +" > "$STAGE/yosys_uart.log" 2>&1 || { + status=$? + cat "$STAGE/yosys_uart.log" + exit "$status" +} +cat "$STAGE/yosys_uart.log" + +echo "=== PLACE+ROUTE (25 MHz, no --timing-allow-fail) ===" +nextpnr-ecp5 --85k --package CABGA381 --json ${TOP}.json --lpf ${LPF} --textcfg ${TOP}.config \ + > "$STAGE/nextpnr_uart.log" 2>&1 || { + status=$? + cat "$STAGE/nextpnr_uart.log" + exit "$status" +} +cat "$STAGE/nextpnr_uart.log" + +echo "=== PACK ===" +ecppack --svf ${TOP}.svf ${TOP}.config ${TOP}.bit > "$STAGE/ecppack_uart.log" 2>&1 || { + status=$? + cat "$STAGE/ecppack_uart.log" + exit "$status" +} +cat "$STAGE/ecppack_uart.log" + +cp "${TOP}.bit" "$STAGE/$BIT_NAME" + +python3 "$SUPPORT" manifest "$STAGE" SHA256SUMS_bridge.txt "$BIT_NAME" +python3 "$SUPPORT" check "$STAGE" SHA256SUMS_bridge.txt + +grep -E 'Max frequency|Slack' "$STAGE/nextpnr_uart.log" | tail -5 > "$STAGE/timing_uart.txt" || true + +python3 "$ROOT/tools/source_provenance.py" --check "$STAGE/SOURCE_MANIFEST_uart.txt" +python3 "$ROOT/tools/atomic_publish.py" "$STAGE" "$OUTDIR" +cat "$OUTDIR/timing_uart.txt" + +echo "=== UART BUILD COMPLETE ===" +ls -l "$OUTDIR/$BIT_NAME" +echo "bitstream: $OUTDIR/$BIT_NAME" +echo "sha256: $(python3 "$SUPPORT" digest "$OUTDIR/$BIT_NAME")" diff --git a/fpga/ulx3s/smoke.config b/fpga/ulx3s/smoke.config new file mode 100644 index 0000000..9034a0b --- /dev/null +++ b/fpga/ulx3s/smoke.config @@ -0,0 +1,1088 @@ +.device LFE5U-85F + +.comment Part: LFE5U-85F-6CABGA381 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R34C3:CIB_DSP +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R37C1:CIB_LR +arc: JA0 E1_H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R46C2:ECLK_L +arc: S2W2_JINCK S2W2_JPADDI + +.tile CIB_R5C125:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C123:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C46:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C47:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C48:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C49:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C50:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C51:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C52:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C53:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C54:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C55:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C56:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C57:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R94C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C71:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C72:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C73:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C74:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C75:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C76:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C77:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C78:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C79:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R94C80:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C81:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C82:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R22C12:EBR_SPINE_UL2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C67:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_HPFE0100 + +.tile MIB_R22C68:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_HPFE0100 + +.tile MIB_R36C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R46C3:LMID_0 +arc: G_LDCC1CLKI G_JPCLKT61 + +.tile MIB_R47C0:PICL0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R48C0:PICL1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R70C67:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_HPFE0100 + +.tile MIB_R70C68:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_HPFE0100 + +.tile MIB_R95C101:PICB0 +unknown: F0B1 + +.tile MIB_R95C102:PICB1 +unknown: F0B1 + +.tile MIB_R95C103:PICB0 +unknown: F0B1 + +.tile MIB_R95C104:PICB1 +unknown: F0B1 + +.tile MIB_R95C105:PICB0 +unknown: F0B1 + +.tile MIB_R95C106:PICB1 +unknown: F0B1 + +.tile MIB_R95C107:PICB0 +unknown: F0B1 + +.tile MIB_R95C108:PICB1 +unknown: F0B1 + +.tile MIB_R95C110:PICB0 +unknown: F0B1 + +.tile MIB_R95C111:PICB1 +unknown: F0B1 + +.tile MIB_R95C112:PICB0 +unknown: F0B1 + +.tile MIB_R95C113:PICB1 +unknown: F0B1 + +.tile MIB_R95C114:PICB0 +unknown: F0B1 + +.tile MIB_R95C115:PICB1 +unknown: F0B1 + +.tile MIB_R95C116:PICB0 +unknown: F0B1 + +.tile MIB_R95C117:PICB1 +unknown: F0B1 + +.tile MIB_R95C119:PICB0 +unknown: F0B1 + +.tile MIB_R95C120:PICB1 +unknown: F0B1 + +.tile MIB_R95C121:PICB0 +unknown: F0B1 + +.tile MIB_R95C122:PICB1 +unknown: F0B1 + +.tile MIB_R95C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R95C96:PICB0 +unknown: F0B1 + +.tile MIB_R95C97:PICB1 +unknown: F0B1 + +.tile MIB_R95C98:PICB0 +unknown: F0B1 + +.tile MIB_R95C99:PICB1 +unknown: F0B1 + +.tile R30C2:PLC2 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C2:PLC2 +arc: H00L0000 V02S0201 +arc: V00B0000 V02S0001 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q6 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C3:PLC2 +arc: S1_V02S0201 E1_H02W0201 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C4:PLC2 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C5:PLC2 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R32C24:PLC2 +word: SLICEB.K0.INIT 1111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R33C3:PLC2 +arc: D3 N1_V02S0201 +arc: F3 F3_SLICE +arc: V01S0100 F3 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R37C3:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile TAP_R30C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + +.tile TAP_R31C13:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 + diff --git a/fpga/ulx3s/smoke.ys b/fpga/ulx3s/smoke.ys new file mode 100644 index 0000000..b33efb9 --- /dev/null +++ b/fpga/ulx3s/smoke.ys @@ -0,0 +1,7 @@ +# Yosys script for minimal smoke (no UART, no ASIC core) +read_verilog -sv smoke_top.sv +hierarchy -check -top smoke_top +proc +check +synth_ecp5 -top smoke_top +write_json smoke.json diff --git a/fpga/ulx3s/smoke_top.sv b/fpga/ulx3s/smoke_top.sv new file mode 100644 index 0000000..87e2165 --- /dev/null +++ b/fpga/ulx3s/smoke_top.sv @@ -0,0 +1,19 @@ +`default_nettype none +/* + * Minimal 25 MHz counter/LED smoke for ULX3S v3.1.8 / LFE5U-85F. + * Purpose: prove reproducible yosys -> nextpnr-ecp5 -> ecppack flow. + * No ASIC core instantiated. No UART. Pure fabric heartbeat. + */ +module smoke_top ( + input wire clk, + output wire led +); + // 25 MHz clock domain. 25-bit counter for visible blink (~0.67 s period). + reg [24:0] cnt; + always @(posedge clk) begin + cnt <= cnt + 1'b1; + end + // Active-low LED on ULX3S: drive low to light. + assign led = ~cnt[24]; +endmodule +`default_nettype wire diff --git a/fpga/ulx3s/uart_bridge.sv b/fpga/ulx3s/uart_bridge.sv new file mode 100644 index 0000000..ff6279b --- /dev/null +++ b/fpga/ulx3s/uart_bridge.sv @@ -0,0 +1,176 @@ +`default_nettype none +/* + * UART <-> LSC-1 pin bridge for ULX3S SRAM smoke. + * - Instantiates exact lean_silicon_lsc1 (no wide bypass). + * - 2-flop sync UART RX at 1 Mbaud (25 MHz / 25). + * - UART TX at 1 Mbaud. + * - Byte buffering + backpressure: only assert RX_VALID when core rx_ready. + * - POR reset synchroniser (2-flop). + * - External ABORT from a framing error or host command byte 0x7f treated as abort pulse. + * + * Pin contract preserved: every byte crosses ui_in / uo_out / uio_* exactly. + */ +module uart_bridge ( + input wire clk, // 25 MHz + input wire uart_rx, // async from FTDI (M1) + output wire uart_tx // to FTDI (L4) +); + // Power-on reset (active-low). The shift register starts at zero, so rst_n + // is genuinely held low for POR_CYCLES edges before it releases. A + // synchroniser that only ever shifts in ones never asserts reset at all, + // which leaves every register in this file and in the core undefined. + localparam integer POR_CYCLES = 8; + reg [POR_CYCLES-1:0] por_shift = {POR_CYCLES{1'b0}}; + always @(posedge clk) por_shift <= {por_shift[POR_CYCLES-2:0], 1'b1}; + wire rst_n = por_shift[POR_CYCLES-1]; + + // UART RX + wire [7:0] uart_rx_data; + wire uart_rx_valid; + wire uart_framing_err; + + uart_rx #( + .CLK_HZ(25_000_000), + .BAUD(1_000_000) + ) urx ( + .clk(clk), + .rst_n(rst_n), + .rx_async(uart_rx), + .rx_data(uart_rx_data), + .rx_valid(uart_rx_valid), + .framing_err(uart_framing_err) + ); + + // UART TX + wire [7:0] uart_tx_data; + wire uart_tx_valid; + wire uart_tx_ready; + + uart_tx #( + .CLK_HZ(25_000_000), + .BAUD(1_000_000) + ) utx ( + .clk(clk), + .rst_n(rst_n), + .tx_data(uart_tx_data), + .tx_valid(uart_tx_valid), + .tx_ready(uart_tx_ready), + .tx_serial(uart_tx) + ); + + // Exact ASIC pin interface (ui/uio) - NO wide ports exposed + wire [7:0] ui_in; + wire [7:0] uo_out; + wire [7:0] uio_in; + wire [7:0] uio_out; + wire [7:0] uio_oe; + + // Bridge control: + // Host drives: uio_in[0]=RX_VALID, uio_in[3]=TX_READY, uio_in[6]=ABORT + // ASIC drives: uio_out[1]=RX_READY, uio_out[2]=TX_VALID, ... + // We sample uio_out (ASIC outputs) and drive uio_in (host inputs). + // + // Both directions use a one-deep buffer whose ready deasserts on the very + // handshake that fills it. That is what makes the ready/valid contract hold + // in both directions: a byte is never presented to a side that has not + // signalled room for it, and never replaced before the far side took it. + + reg abort_q; + + // Framing errors and the explicit 0x7f abort byte both produce a one-cycle + // abort pulse. uart_framing_err and uart_rx_valid are themselves one-cycle + // pulses, so no extra edge detection is needed. + wire rx_byte_ok = uart_rx_valid && !uart_framing_err; + wire rx_is_abort = rx_byte_ok && (uart_rx_data == 8'h7f); + + always @(posedge clk) begin + if (!rst_n) abort_q <= 1'b0; + else abort_q <= uart_framing_err || rx_is_abort; + end + + // ---- host -> core ---------------------------------------------------- + // RX_VALID stays asserted until the core completes the handshake. Sampling + // RX_READY a cycle early and pulsing RX_VALID regardless discards every + // byte that arrives while the core is mid-transaction. + reg rx_full; + reg [7:0] rx_data_q; + reg rx_overrun; + + wire core_rx_ready = uio_out[1]; + wire rx_core_fire = rx_full && core_rx_ready; + wire rx_accept = rx_byte_ok && !rx_is_abort; + + always @(posedge clk) begin + if (!rst_n) begin + rx_full <= 1'b0; + rx_data_q <= 8'h00; + end else if (abort_q) begin + // The buffered byte belongs to the transaction being abandoned. + rx_full <= 1'b0; + end else if (rx_accept) begin + rx_data_q <= uart_rx_data; + rx_full <= 1'b1; + end else if (rx_core_fire) begin + rx_full <= 1'b0; + end + end + + // Sticky observability probe: a byte arrived while the buffer was still + // full and not being drained, so it displaced one the core never read. + // Testbenches assert this stays clear; it drives no logic. + always @(posedge clk) begin + if (!rst_n) rx_overrun <= 1'b0; + else if (rx_accept && rx_full && !rx_core_fire) rx_overrun <= 1'b1; + end + + // ---- core -> host ---------------------------------------------------- + // TX_READY is the buffer-empty flag, so it drops on the same edge the core + // hands a byte over. Mirroring the serialiser's ready one cycle late lets + // the core complete a second handshake while the serialiser is already + // busy, and that byte is overwritten instead of sent. + reg tx_full; + reg [7:0] tx_data_q; + + wire core_tx_valid = uio_out[2]; + wire core_tx_ready = !tx_full; + wire tx_core_fire = core_tx_valid && core_tx_ready; + wire tx_uart_fire = tx_full && uart_tx_ready; + + always @(posedge clk) begin + if (!rst_n) begin + tx_full <= 1'b0; + tx_data_q <= 8'h00; + end else if (abort_q) begin + tx_full <= 1'b0; + end else if (tx_core_fire) begin + tx_data_q <= uo_out; + tx_full <= 1'b1; + end else if (tx_uart_fire) begin + tx_full <= 1'b0; + end + end + + // Wire the exact 8-bit interface + assign ui_in = rx_data_q; + assign uio_in = {1'b0, abort_q, 1'b0, 1'b0, core_tx_ready, 1'b0, 1'b0, rx_full}; + + assign uart_tx_data = tx_data_q; + assign uart_tx_valid = tx_full; + + // Instantiate the exact contract top (MinCore seed, not v1 packet) + lean_silicon_lsc1 asic ( + .ui_in (ui_in), + .uo_out (uo_out), + .uio_in (uio_in), + .uio_out(uio_out), + .uio_oe (uio_oe), + .ena (1'b1), + .clk (clk), + .rst_n (rst_n) + ); + + // Unused uio_oe and other bits are left floating in harness; ASIC drives them. + wire _unused = &{uio_oe, rx_overrun, 1'b0}; + +endmodule +`default_nettype wire diff --git a/fpga/ulx3s/uart_rx.sv b/fpga/ulx3s/uart_rx.sv new file mode 100644 index 0000000..4507241 --- /dev/null +++ b/fpga/ulx3s/uart_rx.sv @@ -0,0 +1,83 @@ +`default_nettype none +/* + * Conservative 1 Mbaud UART RX for 25 MHz clock. + * 2-flop synchronizer on rx line. 8N1, single stop bit. + * Asserts framing_err on stop-bit failure. Drops the byte on framing error. + * rx_valid pulses for one cycle when a clean byte is available. + */ +module uart_rx #( + parameter integer CLK_HZ = 25_000_000, + parameter integer BAUD = 1_000_000 +) ( + input wire clk, + input wire rst_n, + input wire rx_async, + output reg [7:0] rx_data, + output reg rx_valid, + output reg framing_err +); + localparam integer DIV = CLK_HZ / BAUD; + // 2-flop synchronizer + reg rx_m, rx_s; + always @(posedge clk) begin + rx_m <= rx_async; + rx_s <= rx_m; + end + + reg [15:0] div_cnt; + reg [3:0] bit_cnt; + reg [7:0] shift; + reg receiving; + + always @(posedge clk) begin + if (!rst_n) begin + div_cnt <= 0; + bit_cnt <= 0; + shift <= 0; + receiving <= 0; + rx_valid <= 0; + framing_err <= 0; + rx_data <= 0; + end else begin + rx_valid <= 0; + framing_err <= 0; + + if (!receiving) begin + // Wait for start bit (falling edge) + if (rx_s == 1'b0) begin + receiving <= 1'b1; + // Sample in middle of start bit: count DIV/2 + div_cnt <= DIV[15:1]; + bit_cnt <= 0; + end + end else begin + if (div_cnt == DIV-1) begin + div_cnt <= 0; + if (bit_cnt == 0) begin + // Verify start bit still low at sample point + if (rx_s != 1'b0) begin + receiving <= 0; + end else begin + bit_cnt <= bit_cnt + 1'b1; + end + end else if (bit_cnt <= 8) begin + shift[bit_cnt-1] <= rx_s; + bit_cnt <= bit_cnt + 1'b1; + end else begin + // Stop bit + if (rx_s != 1'b1) begin + framing_err <= 1'b1; + end else begin + rx_data <= shift; + rx_valid <= 1'b1; + end + receiving <= 0; + end + end else begin + div_cnt <= div_cnt + 1'b1; + end + end + end + end +endmodule +`default_nettype wire diff --git a/fpga/ulx3s/uart_tx.sv b/fpga/ulx3s/uart_tx.sv new file mode 100644 index 0000000..8f9571c --- /dev/null +++ b/fpga/ulx3s/uart_tx.sv @@ -0,0 +1,64 @@ +`default_nettype none +/* + * Conservative 1 Mbaud UART TX for 25 MHz clock. + * 8N1, single stop bit. tx_ready indicates serializer is idle. + */ +module uart_tx #( + parameter integer CLK_HZ = 25_000_000, + parameter integer BAUD = 1_000_000 +) ( + input wire clk, + input wire rst_n, + input wire [7:0] tx_data, + input wire tx_valid, + output reg tx_ready, + output reg tx_serial +); + localparam integer DIV = CLK_HZ / BAUD; + reg [15:0] div_cnt; + reg [3:0] bit_cnt; + reg [8:0] shift; // {stop, data[7:0]} or start+data handled inline + + always @(posedge clk) begin + if (!rst_n) begin + div_cnt <= 0; + bit_cnt <= 0; + tx_ready <= 1'b1; + tx_serial <= 1'b1; + shift <= 9'h1FF; + end else begin + if (tx_ready) begin + tx_serial <= 1'b1; + if (tx_valid) begin + tx_ready <= 1'b0; + // Load: start bit (0) followed by 8 data bits; stop is implicit high after + shift <= {tx_data, 1'b0}; // LSB first out: we shift right + div_cnt <= 0; + bit_cnt <= 0; + end + end else begin + if (div_cnt == DIV-1) begin + div_cnt <= 0; + // shift out LSB + tx_serial <= shift[0]; + shift <= {1'b1, shift[8:1]}; + // bit_cnt 0 drives the start bit, 1..8 the data bits, and 9 + // the stop bit. Releasing tx_ready at 8 would end data bit 7 + // after a single clock instead of a full baud interval, so a + // receiver samples every zero-valued bit 7 as one. + if (bit_cnt == 9) begin + // The stop bit and the idle level are both high, so the + // ready branch holds this level until the next load. + tx_ready <= 1'b1; + bit_cnt <= 0; + end else begin + bit_cnt <= bit_cnt + 1'b1; + end + end else begin + div_cnt <= div_cnt + 1'b1; + end + end + end + end +endmodule +`default_nettype wire diff --git a/fpga/ulx3s/ulx3s_top.sv b/fpga/ulx3s/ulx3s_top.sv new file mode 100644 index 0000000..294aa34 --- /dev/null +++ b/fpga/ulx3s/ulx3s_top.sv @@ -0,0 +1,38 @@ +`default_nettype none +/* + * ULX3S v3.1.8 top: selects between smoke and UART bridge via parameter. + * Default: UART bridge (P1 deliverable). Smoke is a separate minimal target. + * + * This file is the board-level wrapper. It does NOT widen the ASIC boundary. + */ +module ulx3s_top #( + parameter bit USE_SMOKE = 1'b0 +) ( + input wire clk, // G2 25 MHz + output wire led, // B2 LED0 (active low) + input wire uart_rx, // M1 from FT231X + output wire uart_tx // L4 to FT231X +); + + generate + if (USE_SMOKE) begin : g_smoke + smoke_top u_smoke ( + .clk(clk), + .led(led) + ); + assign uart_tx = 1'b1; // idle + wire _u = uart_rx; + end else begin : g_uart + uart_bridge u_bridge ( + .clk(clk), + .uart_rx(uart_rx), + .uart_tx(uart_tx) + ); + // Optional heartbeat on LED: toggle slowly when bridge idle + reg [23:0] hb; + always @(posedge clk) hb <= hb + 1'b1; + assign led = ~hb[23]; // gentle heartbeat; real activity is UART + end + endgenerate +endmodule +`default_nettype wire diff --git a/fpga/ulx3s/ulx3s_v318_smoke.lpf b/fpga/ulx3s/ulx3s_v318_smoke.lpf new file mode 100644 index 0000000..1561cc2 --- /dev/null +++ b/fpga/ulx3s/ulx3s_v318_smoke.lpf @@ -0,0 +1,20 @@ +# ULX3S v3.1.8 (LFE5U-85F) minimal smoke constraints +# Source: pin-subset hypothesis derived from ulx3s-misc v316 LPF for v3.1.6/3.1.7 +# Applicability: v3.1.8; G2/B2/M1/L4 are stable across v3.x; full LPF not reproduced here. +# This file intentionally contains only the pins used by the smoke design. +# Clock: 25 MHz onboard oscillator +LOCATE COMP "clk" SITE "G2"; +IOBUF PORT "clk" IO_TYPE=LVCMOS33; +# Without this the router falls back to its 12 MHz default, so a passing +# nextpnr timing report says nothing about closure at the real board clock. +FREQUENCY PORT "clk" 25.000000 MHz; +# LED0 (active low on ULX3S) +LOCATE COMP "led" SITE "B2"; +IOBUF PORT "led" IO_TYPE=LVCMOS33; +# UART (US1 FT231X): FPGA RX = M1 (host TX), FPGA TX = L4 (host RX) +LOCATE COMP "uart_rx" SITE "M1"; +IOBUF PORT "uart_rx" IO_TYPE=LVCMOS33 PULLMODE=UP; +LOCATE COMP "uart_tx" SITE "L4"; +IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33 DRIVE=4; +# Explicit: SDRAM pins are NOT constrained or used by this design. +# Never pass -f to any flash tool for this SRAM-only smoke. diff --git a/fpga_harness/BUILD_PLAN.md b/fpga_harness/BUILD_PLAN.md index 4938b8b..cc49eca 100644 --- a/fpga_harness/BUILD_PLAN.md +++ b/fpga_harness/BUILD_PLAN.md @@ -1,9 +1,21 @@ # Harness build and check plan -An ordered plan from what runs today to what would constitute real hardware -evidence. Stages 0–1 are executable now and are wired into `make check`. -Stages 2 onward are **not** implemented and are deliberately not faked; each -lists its entry condition so it cannot be skipped. +## Current status + +The repository now contains source-built, archived ULX3S smoke and UART +bitstreams, their 25 MHz timing/provenance evidence, an LPF, build recipes, and +a host UART byte driver; see [the ULX3S evidence record](../docs/ULX3S_SMOKE_AND_UART.md). +None of those artifacts is hardware validation: this repository records no +board programming or captured board byte exchange, so the data path remains +**unvalidated**. + +## Historical planning snapshot (pre-deliverable) + +The ordered stage descriptions below are retained as the pre-deliverable +milestone plan. Their current-tense statements about absent bitstreams, +constraints, synthesis, and host drivers describe that historical snapshot, +not the current repository. They remain useful for the distinction between +source-built evidence and the real-hardware evidence still required. The milestone this serves is `ulx3s_pin_harness` in `planning/milestones.yaml`, which depends on `host_packet_runtime`. That dependency is the reason this lane @@ -50,10 +62,12 @@ three are *visibility*, only the fourth is *behaviour*. | `datapath` | did host bytes actually cross the 8-bit ready/valid pins and produce the expected responses? | — this is the only level that would be evidence | `datapath` can never be satisfied by this script. It reports `not-validated` -unconditionally and names its four missing prerequisites, because the repository -contains no harness bitstream, no `.lpf`, no host byte driver, and no captured -byte log. `--require datapath` therefore always exits non-zero. A test asserts -this holds even when the toolchain, USB, and JTAG levels are all fully +unconditionally because it cannot establish the remaining hardware evidence: +no board has been programmed from this repository and no captured board +request/response byte log exists. The source-built bitstreams, LPF, build +recipes, and host UART driver are archived deliverables, not substitutes for +that evidence. `--require datapath` therefore always exits non-zero. A test +asserts this holds even when the toolchain, USB, and JTAG levels are all fully satisfied, which is exactly the confusion this lane exists to prevent. Raising `datapath` requires committing real hardware logs and the code that diff --git a/fpga_harness/INVENTORY.md b/fpga_harness/INVENTORY.md index c255fde..ac89f5b 100644 --- a/fpga_harness/INVENTORY.md +++ b/fpga_harness/INVENTORY.md @@ -1,12 +1,18 @@ -# ULX3S/ECP5 harness inventory - -Inventory of what the repository actually contains for a ULX3S/ECP5 harness, -taken from the tree at the commit this document was added on. Everything below -is either a file path that exists, a literal read out of a source file, or an -explicitly labelled unknown. No item here is hardware evidence: no bitstream -has been built and no board has been driven. See [BUILD_PLAN](BUILD_PLAN.md) -for what would have to happen first, and [BOUNDARY](BOUNDARY.md) for the pin -rule the harness may not break. +# ULX3S/ECP5 harness inventory — historical snapshot + +This is the pre-deliverable inventory, retained to record the original gap +analysis. Its statements that bitstreams, constraints, build recipes, and the +UART bridge do not exist describe the tree when this document was added; they +are **not** current repository status. The current tree has source-built, +archived smoke/UART deliverables under `fpga/ulx3s/` and +`results/ulx3s-smoke-uart-20260725/`; see +[ULX3S_SMOKE_AND_UART.md](../docs/ULX3S_SMOKE_AND_UART.md). + +Those deliverables are not hardware evidence. No board has been programmed or +validated from this repository, and no captured board byte-exchange log exists. +The data path is therefore **unvalidated**. See [BUILD_PLAN](BUILD_PLAN.md) for +the current status and [BOUNDARY](BOUNDARY.md) for the pin rule the harness may +not break. ## 1. Files that exist today diff --git a/fpga_harness/README.md b/fpga_harness/README.md index f42cbf7..82f7784 100644 --- a/fpga_harness/README.md +++ b/fpga_harness/README.md @@ -6,8 +6,9 @@ beat; internal wide datapaths may buffer packets but may not bypass those pins. Mac-host software owns program storage, VM memory, hints, witnesses, pointer resolution, deferred equality, inversion assistance, BLAKE3, traces, and proofs. -The directory intentionally contains an interface contract and no fabricated -ULX3S bitstream or USB implementation. +The directory contains the interface contract plus an archived source-built +ULX3S smoke/UART bitstream deliverable. It does not contain a USB implementation +or evidence of any board being programmed or validated. ## Contents @@ -16,17 +17,19 @@ ULX3S bitstream or USB implementation. | [INVENTORY.md](INVENTORY.md) | What exists, what is absent, toolchain, pins/clocks/resets, explicit unknowns | | [BOUNDARY.md](BOUNDARY.md) | Normative pin-accurate boundary and the prohibition on wide bypasses | | [BUILD_PLAN.md](BUILD_PLAN.md) | Ordered plan: what runs today, and the entry condition for each unimplemented stage | -| `rtl/lean_silicon_lsc1_pins.sv` | Port-list-only pin contract; no bitstream, no handshake yet | +| `rtl/lean_silicon_lsc1_pins.sv` | Port-list-only pin contract; no handshake implementation in this harness path | +| [`../docs/ULX3S_SMOKE_AND_UART.md`](../docs/ULX3S_SMOKE_AND_UART.md) | Archived source-build artefacts, provenance, and explicit hardware limits | | `boundary_check.py` | Structural pin/no-bypass check, run by `make check` | | `board_detect.py` | Layered board detection that never claims data-path validation | | `test_boundary_check.py`, `test_board_detect.py` | Deterministic tests; no board required | ## Status -No bitstream has been built and no board has been driven from this repository. -The data path is **unvalidated**, and `board_detect.py` reports it that way even -when a real board is visible over USB and JTAG — tool, USB, and JTAG visibility -are not evidence that bytes cross the interface correctly. +Smoke and UART bitstreams have been source-built and archived; no board has been +driven or validated from this repository. The data path is **unvalidated**, and +`board_detect.py` reports it that way even when a real board is visible over USB +and JTAG — tool, USB, and JTAG visibility are not evidence that bytes cross the +interface correctly. ```sh make fpga-boundary # structural boundary check (gating) diff --git a/fpga_harness/board_detect.py b/fpga_harness/board_detect.py index 3d27c6f..b6f0ff5 100644 --- a/fpga_harness/board_detect.py +++ b/fpga_harness/board_detect.py @@ -10,11 +10,11 @@ datapath host bytes actually crossed the exact LSC-1 8-bit ready/valid pins and produced the expected response bytes -Only ``datapath`` is evidence that the harness works. This tool can never -report it as satisfied: the repository contains no harness bitstream and no -recorded byte-exchange log, so there is nothing to validate against. Raising -that level requires real hardware logs committed by a later change, not a -different exit code here. +Only ``datapath`` is evidence that the harness works. This tool can never +report it as satisfied: source-built archival bitstreams and a host UART driver +exist, but the repository has no programmed-board byte-exchange log to validate +against. Raising that level requires real hardware logs committed by a later +change, not a different exit code here. The ``usb`` and ``jtag`` probes are host-specific: Linux has sysfs, macOS has the IOKit registry, and ``openFPGALoader --detect`` has to be told the ULX3S @@ -58,12 +58,11 @@ BUILD_TOOLS = ("yosys", "nextpnr-ecp5", "ecppack") LOAD_TOOLS = ("openFPGALoader", "fujprog") -# Prerequisites that do not exist in this repository. Listed so the datapath -# verdict names what is missing instead of only refusing. +# Evidence prerequisites that this reporting-only detector cannot establish. +# Source-built bitstreams and a host UART driver exist; no board programming or +# captured byte exchange has been recorded in this repository. DATAPATH_PREREQUISITES = ( - "a synthesised ULX3S bitstream for a harness top-level", - "an ECP5 pin constraint file (.lpf) mapping the 8-bit interface to board pins", - "a host-side byte-exchange driver for the ready/valid handshake", + "a real ULX3S board programmed with a checksum-verified archived bitstream", "a recorded request/response byte log captured from real hardware", ) @@ -503,7 +502,7 @@ def _probe_jtag(env: Environment) -> list[Finding]: def _probe_datapath(_env: Environment) -> list[Finding]: - """Always unvalidated: there is nothing in-repo to validate against.""" + """Always unvalidated: no physical board byte-exchange evidence is archived.""" missing = "; ".join(DATAPATH_PREREQUISITES) return [ Finding( diff --git a/fpga_harness/test_artefact_provenance.py b/fpga_harness/test_artefact_provenance.py new file mode 100644 index 0000000..f189003 --- /dev/null +++ b/fpga_harness/test_artefact_provenance.py @@ -0,0 +1,313 @@ +"""The evidence archive must identify the sources that actually produced it. + +`docs/ULX3S_SMOKE_AND_UART.md` claimed the bitstreams came from the branch's +pre-feature base revision. That revision contains no `fpga/ulx3s` file at all, +so the claim could not be checked and the artefacts could not be rebuilt from +it: an evidence archive that cannot name its own source proves nothing. + +The build inputs are parsed out of the build scripts rather than restated here, +so adding a source to a build without recording it fails instead of silently +widening the gap between what was built and what was declared. No board and no +FPGA toolchain are involved. +""" + +from __future__ import annotations + +import os +import re +import shutil +import subprocess +import tempfile +import unittest +from hashlib import sha256 +from pathlib import Path + +ROOT = Path(__file__).resolve().parent.parent +RECORDER = ROOT / "tools" / "source_provenance.py" +ULX3S = ROOT / "fpga" / "ulx3s" +DOC = ROOT / "docs" / "ULX3S_SMOKE_AND_UART.md" +RESULTS = ROOT / "results" / "ulx3s-smoke-uart-20260725" + +BUILDS = { + "SOURCE_MANIFEST.txt": ULX3S / "build_smoke.sh", + "SOURCE_MANIFEST_uart.txt": ULX3S / "build_uart.sh", +} + + +def _shell_var(text: str, name: str) -> str: + match = re.search(rf"^{name}=(.+)$", text, re.MULTILINE) + assert match, f"{name} not found in build script" + return match.group(1).strip().strip('"') + + +def _recorder_args(text: str) -> list[str]: + """The still-unexpanded arguments a build hands to the provenance recorder.""" + match = re.search(r"source_provenance\.py\"(?:\\\n|[^\n])*", text) + assert match, "build script no longer invokes the provenance recorder" + # Past the recorder itself and the manifest it writes, every argument is an + # input whose digest the archive will carry. + return match.group(0).replace("\\\n", " ").split()[2:] + + +def build_inputs(script: Path) -> set[str]: + """Repo-relative inputs a build script records provenance for. + + Read back out of the recorder invocation rather than restated here, so a + build that stops recording one of its inputs fails instead of silently + narrowing what the archive claims to cover. + """ + text = script.read_text() + sources = re.search(r'SOURCES="([^"]*)"', text, re.DOTALL) + expansions = { + '"$LPF"': [_shell_var(text, "LPF")], + '"${TOP}.sv"': [_shell_var(text, "TOP") + ".sv"], + '"$RECIPE"': [script.name], + '"$SUPPORT"': [_shell_var(text, "SUPPORT")], + '"$ROOT/tools/atomic_publish.py"': ["../../tools/atomic_publish.py"], + '"$ROOT/tools/source_provenance.py"': ["../../tools/source_provenance.py"], + "$SOURCES": sources.group(1).replace("\\\n", " ").split() if sources else [], + } + names: list[str] = [] + for arg in _recorder_args(text): + assert arg in expansions, f"{script.name}: unrecognised recorder argument {arg}" + assert expansions[arg], f"{script.name}: {arg} expands to no input" + names += expansions[arg] + return {(ULX3S / n).resolve().relative_to(ROOT).as_posix() for n in names} + + +def manifest_digests(name: str) -> dict[str, str]: + entries = {} + for line in (RESULTS / name).read_text().splitlines(): + parts = line.split() + if len(parts) == 2 and re.fullmatch(r"[0-9a-f]{64}", parts[0]): + entries[parts[1]] = parts[0] + return entries + + +def doc_revision(label: str) -> str: + match = re.search(rf"{label}[^`]*`([0-9a-f]{{7,40}})`", DOC.read_text()) + assert match, f"docs no longer record a revision for {label!r}" + return match.group(1) + + +def _blob_at(rev: str, path: str) -> bytes | None: + result = subprocess.run( + ["git", "cat-file", "blob", f"{rev}:{path}"], + cwd=ROOT, + stdout=subprocess.PIPE, + stderr=subprocess.DEVNULL, + ) + return result.stdout if result.returncode == 0 else None + + +class BuildInputParsingTest(unittest.TestCase): + """Guards every other test here from passing vacuously on an empty set.""" + + def test_both_builds_declare_their_sources(self): + for manifest, script in BUILDS.items(): + with self.subTest(script=script.name): + inputs = build_inputs(script) + self.assertGreaterEqual(len(inputs), 2, f"{script.name}: {inputs}") + self.assertTrue(any(i.endswith(".lpf") for i in inputs)) + + def test_declared_sources_exist(self): + for script in BUILDS.values(): + for rel in build_inputs(script): + with self.subTest(source=rel): + self.assertTrue((ROOT / rel).is_file(), rel) + + def test_each_build_records_its_own_recipe(self): + # Identical RTL built through an edited recipe yields a different + # bitstream, so a manifest blind to the recipe can report a match for an + # artefact no revision can reproduce. + for script in BUILDS.values(): + with self.subTest(script=script.name): + self.assertRegex( + script.read_text(), + re.compile(r'^RECIPE=\$\(basename -- "\$0"\)$', re.M), + ) + rel = script.resolve().relative_to(ROOT).as_posix() + self.assertIn(rel, build_inputs(script)) + + def test_uart_build_pulls_in_the_asic_core(self): + # The bridge is only evidence if it wraps the real core, not a stub. + inputs = build_inputs(ULX3S / "build_uart.sh") + self.assertIn("asic_core/rtl/lean_silicon_lsc1.sv", inputs) + + +class SourceManifestTest(unittest.TestCase): + """Content anchor: valid without git history, so CI checks it too.""" + + def test_manifest_covers_exactly_the_build_inputs(self): + for manifest, script in BUILDS.items(): + with self.subTest(manifest=manifest): + self.assertEqual(set(manifest_digests(manifest)), build_inputs(script)) + + def test_manifest_digests_match_the_working_tree(self): + for manifest in BUILDS: + for rel, digest in manifest_digests(manifest).items(): + with self.subTest(source=rel): + self.assertEqual( + sha256((ROOT / rel).read_bytes()).hexdigest(), + digest, + f"{rel} changed since {manifest} was recorded; rebuild", + ) + + def test_manifest_records_whether_inputs_matched_the_revision(self): + for manifest in BUILDS: + with self.subTest(manifest=manifest): + text = (RESULTS / manifest).read_text() + self.assertRegex(text, re.compile(r"^revision: [0-9a-f]{40}$", re.M)) + self.assertRegex( + text, re.compile(r"^inputs-match-revision: (yes|no)$", re.M) + ) + + +class RecorderMatchFlagTest(unittest.TestCase): + """`inputs-match-revision` must never claim more than was actually compared. + + Driven against throwaway trees rather than the repo, because the interesting + states -- no git at all, and a modified input -- cannot be staged here. + """ + + def _tree(self) -> Path: + root = Path(tempfile.mkdtemp()).resolve() + self.addCleanup(shutil.rmtree, root, True) + (root / "tools").mkdir() + shutil.copy(RECORDER, root / "tools") + (root / "src").mkdir() + (root / "src" / "a.sv").write_text("module a; endmodule\n") + return root + + def _record(self, root: Path) -> dict[str, str]: + env = dict(os.environ, GIT_CEILING_DIRECTORIES=str(root.parent)) + subprocess.run( + ["python3", str(root / "tools" / "source_provenance.py"), "out.txt", "a.sv"], + cwd=root / "src", + check=True, + stdout=subprocess.DEVNULL, + env=env, + ) + fields = {} + for line in (root / "src" / "out.txt").read_text().splitlines(): + key, _, value = line.partition(": ") + if value: + fields[key] = value + return fields + + def _git_tree(self) -> Path: + root = self._tree() + for args in ( + ["init", "-q"], + ["config", "user.email", "t@example.invalid"], + ["config", "user.name", "t"], + ["add", "-A"], + ["-c", "commit.gpgsign=false", "commit", "-qm", "x"], + ): + result = subprocess.run(["git", *args], cwd=root, capture_output=True) + if result.returncode != 0: + self.skipTest(f"git {args[0]} unavailable: {result.stderr!r}") + return root + + def test_unidentified_revision_is_not_reported_as_a_match(self): + # The defect: with no revision, every comparison was skipped and the + # dirty flag stayed false, so the archive claimed its inputs matched a + # revision that had never been identified. + fields = self._record(self._tree()) + self.assertEqual(fields["revision"], "unknown") + self.assertNotEqual(fields["inputs-match-revision"], "yes") + + def test_committed_inputs_report_a_match(self): + fields = self._record(self._git_tree()) + self.assertRegex(fields["revision"], r"^[0-9a-f]{40}$") + self.assertEqual(fields["inputs-match-revision"], "yes") + + def test_modified_input_reports_no_match(self): + root = self._git_tree() + (root / "src" / "a.sv").write_text("module b; endmodule\n") + fields = self._record(root) + self.assertRegex(fields["revision"], r"^[0-9a-f]{40}$") + self.assertEqual(fields["inputs-match-revision"], "no") + + def test_a_match_is_only_ever_claimed_against_a_named_revision(self): + # Generalises the three cases above: whatever the tree looks like, "yes" + # is only honest when a real revision was resolved to compare against. + for name, make in (("no-git", self._tree), ("git", self._git_tree)): + with self.subTest(tree=name): + fields = self._record(make()) + if fields["inputs-match-revision"] == "yes": + self.assertRegex(fields["revision"], r"^[0-9a-f]{40}$") + + +class PrePublishRevalidationTest(unittest.TestCase): + def _tree(self) -> tuple[Path, Path, Path]: + root = Path(tempfile.mkdtemp()).resolve() + self.addCleanup(shutil.rmtree, root, True) + (root / "tools").mkdir() + shutil.copy(RECORDER, root / "tools") + source = root / "input.sv" + source.write_text("module input_file; endmodule\n") + digest = sha256(source.read_bytes()).hexdigest() + manifest = root / "manifest.txt" + manifest.write_text( + "=== SOURCE PROVENANCE ===\n" + f"{digest} input.sv\n" + ) + return root, source, manifest + + def _check(self, root: Path, manifest: Path) -> subprocess.CompletedProcess[str]: + return subprocess.run( + [ + "python3", + str(root / "tools" / "source_provenance.py"), + "--check", + str(manifest), + ], + cwd=root, + text=True, + capture_output=True, + ) + + def test_unchanged_input_is_accepted(self): + root, _source, manifest = self._tree() + self.assertEqual(self._check(root, manifest).returncode, 0) + + def test_input_changed_after_manifest_is_rejected(self): + root, source, manifest = self._tree() + source.write_text("module changed_during_build; endmodule\n") + result = self._check(root, manifest) + self.assertNotEqual(result.returncode, 0) + self.assertIn("CHANGED DURING BUILD", result.stderr) + + +class SquashSafeProvenanceTest(unittest.TestCase): + """Evidence remains verifiable when a squash discards its source commit.""" + + def test_artefact_revision_is_not_the_branch_base(self): + self.assertNotEqual( + doc_revision("Artefact source revision"), + doc_revision("Branch base"), + "the pre-feature base cannot be the artefact source", + ) + + def test_manifests_verify_without_the_recorded_git_object(self): + # A squash has no obligation to retain a feature-only object. The + # archived source digests, not `git cat-file :path`, are + # therefore the durable verification mechanism. + with tempfile.TemporaryDirectory() as temporary: + root = Path(temporary) + for manifest, script in BUILDS.items(): + copied = root / manifest + copied.write_text((RESULTS / manifest).read_text()) + for rel, digest in manifest_digests(manifest).items(): + target = root / rel + target.parent.mkdir(parents=True, exist_ok=True) + shutil.copyfile(ROOT / rel, target) + self.assertEqual(sha256(target.read_bytes()).hexdigest(), digest) + # There is intentionally no .git directory and no source SHA + # object here; all verification above is content-addressed. + self.assertFalse((root / ".git").exists()) + + +if __name__ == "__main__": + unittest.main() diff --git a/fpga_harness/test_atomic_publish.py b/fpga_harness/test_atomic_publish.py new file mode 100644 index 0000000..d312982 --- /dev/null +++ b/fpga_harness/test_atomic_publish.py @@ -0,0 +1,125 @@ +"""Regression tests for all-or-nothing ULX3S archive publication.""" + +from __future__ import annotations + +import errno +import importlib.util +import os +from pathlib import Path +import shutil +import signal +import subprocess +import sys +import tempfile +import time +import unittest +from unittest import mock + + +ROOT = Path(__file__).resolve().parents[1] +SCRIPT = ROOT / "tools" / "atomic_publish.py" +SPEC = importlib.util.spec_from_file_location("atomic_publish", SCRIPT) +assert SPEC is not None and SPEC.loader is not None +atomic_publish = importlib.util.module_from_spec(SPEC) +SPEC.loader.exec_module(atomic_publish) + + +def snapshot(directory: Path) -> dict[str, bytes]: + return { + path.relative_to(directory).as_posix(): path.read_bytes() + for path in directory.rglob("*") + if path.is_file() + } + + +class AtomicPublishTest(unittest.TestCase): + def setUp(self) -> None: + self.tempdir = tempfile.TemporaryDirectory() + self.parent = Path(self.tempdir.name) + self.destination = self.parent / "archive" + self.staged = self.parent / "stage" + self.destination.mkdir() + self.staged.mkdir() + (self.destination / "bitstream.bit").write_bytes(b"old bitstream") + (self.destination / "SHA256SUMS").write_bytes(b"old manifest") + (self.staged / "bitstream.bit").write_bytes(b"new bitstream") + (self.staged / "SHA256SUMS").write_bytes(b"new manifest") + + def tearDown(self) -> None: + self.tempdir.cleanup() + + def test_failed_exchange_keeps_the_complete_old_archive(self) -> None: + old = snapshot(self.destination) + with mock.patch.object( + atomic_publish, "_exchange", side_effect=OSError(errno.EIO, "injected") + ): + with self.assertRaises(OSError): + atomic_publish.publish(self.staged, self.destination) + self.assertEqual(snapshot(self.destination), old) + self.assertEqual(snapshot(self.staged)["bitstream.bit"], b"new bitstream") + + def test_mutation_guard_rejects_copy_before_exchange(self) -> None: + """A failed swap must not have copied even one staged archive member.""" + old = snapshot(self.destination) + with mock.patch.object( + atomic_publish, "_exchange", side_effect=OSError(errno.EIO, "injected") + ): + with self.assertRaises(OSError): + atomic_publish.publish(self.staged, self.destination) + self.assertEqual(old, snapshot(self.destination)) + self.assertNotEqual(snapshot(self.staged), snapshot(self.destination)) + + def test_interruption_before_exchange_keeps_the_complete_old_archive(self) -> None: + old = snapshot(self.destination) + pause_file = self.parent / "paused" + environment = os.environ | {"ATOMIC_PUBLISH_TEST_PAUSE_FILE": str(pause_file)} + process = subprocess.Popen( + [sys.executable, str(SCRIPT), str(self.staged), str(self.destination)], + env=environment, + ) + try: + deadline = time.monotonic() + 5 + while not pause_file.exists() and time.monotonic() < deadline: + time.sleep(0.01) + self.assertTrue(pause_file.exists(), "publisher did not reach interruption point") + process.send_signal(signal.SIGTERM) + self.assertEqual(process.wait(timeout=5), -signal.SIGTERM) + finally: + if process.poll() is None: + process.kill() + process.wait() + self.assertEqual(snapshot(self.destination), old) + + def test_macos_uses_renameatx_np_when_linux_renameat2_is_absent(self) -> None: + calls: list[tuple[object, ...]] = [] + + class DarwinLibc: + renameat2 = None + + @staticmethod + def renameatx_np(*args: object) -> int: + calls.append(args) + return 0 + + with mock.patch.object(atomic_publish.ctypes, "CDLL", return_value=DarwinLibc()): + atomic_publish._exchange(self.staged, self.destination) + self.assertEqual(len(calls), 1) + self.assertEqual(calls[0][0], atomic_publish.AT_FDCWD_DARWIN) + self.assertEqual(calls[0][2], atomic_publish.AT_FDCWD_DARWIN) + self.assertEqual(calls[0][-1], atomic_publish.RENAME_SWAP) + + def test_no_atomic_exchange_api_fails_without_mutating_archive(self) -> None: + old = snapshot(self.destination) + + class NoExchangeLibc: + renameat2 = None + renameatx_np = None + + with mock.patch.object(atomic_publish.ctypes, "CDLL", return_value=NoExchangeLibc()): + with self.assertRaisesRegex(OSError, "atomic directory exchange"): + atomic_publish.publish(self.staged, self.destination) + self.assertEqual(snapshot(self.destination), old) + + +if __name__ == "__main__": + unittest.main() diff --git a/fpga_harness/test_portable_build_support.py b/fpga_harness/test_portable_build_support.py new file mode 100644 index 0000000..5eb89b7 --- /dev/null +++ b/fpga_harness/test_portable_build_support.py @@ -0,0 +1,137 @@ +"""Board-free regression tests for macOS-compatible ULX3S build support.""" + +from __future__ import annotations + +import os +from pathlib import Path +import shutil +import signal +import subprocess +import sys +import tempfile +import time +import unittest + + +ROOT = Path(__file__).resolve().parents[1] +SUPPORT = ROOT / "tools" / "portable_build_support.py" + + +class PortableBuildSupportTest(unittest.TestCase): + def setUp(self) -> None: + self.tempdir = tempfile.TemporaryDirectory() + self.work = Path(self.tempdir.name) + + def tearDown(self) -> None: + self.tempdir.cleanup() + + def command(self, *args: str, **kwargs: object) -> subprocess.CompletedProcess[str]: + return subprocess.run( + [sys.executable, str(SUPPORT), *args], text=True, capture_output=True, **kwargs + ) + + def test_digest_manifest_detects_mutation_without_sha256sum(self) -> None: + archive = self.work / "archive" + archive.mkdir() + (archive / "artifact.bit").write_bytes(b"original") + self.assertEqual(self.command("manifest", str(archive), "SHA256SUMS", "artifact.bit").returncode, 0) + self.assertEqual(self.command("check", str(archive), "SHA256SUMS").returncode, 0) + (archive / "artifact.bit").write_bytes(b"mutated") + broken = self.command("check", str(archive), "SHA256SUMS") + self.assertNotEqual(broken.returncode, 0) + self.assertIn("artifact.bit: FAILED", broken.stderr) + + def test_check_rejects_an_empty_manifest(self) -> None: + archive = self.work / "archive" + archive.mkdir() + (archive / "SHA256SUMS").write_text("", encoding="ascii") + + result = self.command("check", str(archive), "SHA256SUMS") + + self.assertNotEqual(result.returncode, 0) + self.assertIn("SHA256SUMS: FAILED (no well-formed checksum entries)", result.stderr) + + def test_check_rejects_manifest_with_no_well_formed_entries(self) -> None: + archive = self.work / "archive" + archive.mkdir() + (archive / "SHA256SUMS").write_text("not a checksum entry\n", encoding="ascii") + + result = self.command("check", str(archive), "SHA256SUMS") + + self.assertNotEqual(result.returncode, 0) + self.assertIn("SHA256SUMS: FAILED (no well-formed checksum entries)", result.stderr) + + def test_lock_is_cross_process_and_released_after_interruption(self) -> None: + lock = self.work / "publish.lock" + marker = self.work / "started" + sleeper = self.work / "sleeper.py" + sleeper.write_text( + "from pathlib import Path\nimport sys,time\nPath(sys.argv[1]).touch()\ntime.sleep(30)\n", + encoding="utf-8", + ) + process = subprocess.Popen( + [sys.executable, str(SUPPORT), "lock", str(lock), "--", sys.executable, str(sleeper), str(marker)] + ) + try: + deadline = time.monotonic() + 5 + while not marker.exists() and time.monotonic() < deadline: + time.sleep(0.01) + self.assertTrue(marker.exists(), "lock holder did not start") + blocked = subprocess.Popen( + [sys.executable, str(SUPPORT), "lock", str(lock), "--", sys.executable, "-c", "raise SystemExit(0)"], + ) + time.sleep(0.1) + self.assertIsNone(blocked.poll(), "second publisher acquired a held lock") + process.send_signal(signal.SIGTERM) + process.wait(timeout=5) + self.assertEqual(blocked.wait(timeout=5), 0) + finally: + for child in (process, locals().get("blocked")): + if child is not None and child.poll() is None: + child.kill() + child.wait() + + def test_both_builds_run_with_failing_flock_and_sha256sum_mocks(self) -> None: + """Reproduce a stock-macOS-like tool gap using deterministic board-free tools.""" + repo = self.work / "repo" + shutil.copytree(ROOT, repo, ignore=shutil.ignore_patterns(".git", "__pycache__")) + mocks = self.work / "mock-bin" + mocks.mkdir() + mock = mocks / "tool" + mock.write_text( + "#!/usr/bin/env python3\n" + "import pathlib,sys\n" + "name=pathlib.Path(sys.argv[0]).name\n" + "if name in ('flock','sha256sum'):\n raise SystemExit('non-portable command used: '+name)\n" + "if name == 'yosys':\n" + " if '-V' not in sys.argv:\n p=sys.argv[sys.argv.index('-p')+1]; out=p.split('write_json ')[1].split()[0]; pathlib.Path(out).write_text('{}')\n" + "elif name == 'nextpnr-ecp5':\n" + " if '--version' not in sys.argv:\n out=sys.argv[sys.argv.index('--textcfg')+1]; pathlib.Path(out).write_text('config'); print('Max frequency for clock: 25.00 MHz')\n" + "elif name == 'ecppack':\n" + " if '--version' not in sys.argv:\n pathlib.Path(sys.argv[sys.argv.index('--svf')+1]).write_text('svf'); pathlib.Path(sys.argv[-1]).write_bytes(b'bit')\n" + "elif name == 'grep': pass\n", + encoding="utf-8", + ) + mock.chmod(0o755) + for name in ("yosys", "nextpnr-ecp5", "ecppack", "flock", "sha256sum"): + (mocks / name).symlink_to(mock.name) + environment = os.environ | {"PATH": f"{mocks}:{os.environ['PATH']}", "OSS_CAD_BIN": "/absent"} + for script, manifest in (("build_smoke.sh", "SHA256SUMS"), ("build_uart.sh", "SHA256SUMS_bridge.txt")): + result = subprocess.run( + ["/bin/sh", str(repo / "fpga" / "ulx3s" / script)], + cwd=repo, + env=environment, + text=True, + capture_output=True, + ) + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + verified = subprocess.run( + [sys.executable, str(repo / "tools" / "portable_build_support.py"), "check", str(repo / "results" / "ulx3s-smoke-uart-20260725"), manifest], + text=True, + capture_output=True, + ) + self.assertEqual(verified.returncode, 0, verified.stdout + verified.stderr) + + +if __name__ == "__main__": + unittest.main() diff --git a/fpga_harness/test_ulx3s_uart.py b/fpga_harness/test_ulx3s_uart.py new file mode 100644 index 0000000..2dec4c1 --- /dev/null +++ b/fpga_harness/test_ulx3s_uart.py @@ -0,0 +1,819 @@ +"""Tests for the ULX3S UART driver's response checking. + +The negative cases carry the weight here. A driver that prints a board's reply +and exits zero looks identical to a working one in CI logs, so these tests feed +the driver a complete, well-formed, *wrong* 16-byte MUL response and require a +non-zero exit. No serial port and no board are involved. +""" + +from __future__ import annotations + +import math +import re +import shlex +import threading +import time +import unittest +from pathlib import Path +from unittest import mock + +import ulx3s_uart +from ulx3s_uart import expected_mul + +_STREAM_ALU = ( + Path(__file__).resolve().parent.parent + / "asic_core" + / "rtl" + / "leanvm_b_stream_alu.sv" +) + +# Same vector the RTL testbench uses, so the host tool and the simulation are +# checked against one shared expectation. +MUL_A = bytes.fromhex("112233445566778899aabbccddeeff01") +MUL_B = bytes.fromhex("02000000000000000000000000000000") +MUL_EXPECTED = bytes.fromhex("22446688aaccee1033557799bbddff03") + + +class FakeSerial: + """Minimal stand-in that replays a canned reply once a command is complete.""" + + def __init__(self, response: bytes, command_len: int) -> None: + self._response = response + self._command_len = command_len + self._written = bytearray() + self._pending = bytearray() + self.closed = False + + @property + def in_waiting(self) -> int: + return len(self._pending) + + def write(self, data: bytes) -> int: + self._written.extend(data) + if len(self._written) == self._command_len: + self._pending.extend(self._response) + return len(data) + + def flush(self) -> None: + pass + + def read(self, n: int = 1) -> bytes: + chunk = bytes(self._pending[:n]) + del self._pending[:n] + return chunk + + def reset_input_buffer(self) -> None: + self._pending.clear() + + def reset_output_buffer(self) -> None: + self._written.clear() + + def close(self) -> None: + self.closed = True + + @property + def written(self) -> bytes: + return bytes(self._written) + + +class IdleSerial: + """An idle port whose configured blocking read must never be called.""" + + in_waiting = 0 + + def read(self, _n: int = 1) -> bytes: + raise AssertionError("drain attempted a blocking read on an idle port") + + +def run_status(response: bytes) -> int: + """Run the driver's status path against a canned reply.""" + fake = FakeSerial(response, command_len=2) # ABORT then STATUS + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake): + return ulx3s_uart.main(["--port", "/dev/null", "--tx", "status"]) + + +def run_mul(response: bytes) -> int: + """Run the driver's mul path against a canned 16-byte reply.""" + fake = FakeSerial(response, command_len=1 + 1 + 32) + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake): + return ulx3s_uart.main( + ["--port", "/dev/null", "--tx", "mul", "--payload", (MUL_A + MUL_B).hex()] + ) + + +class ExpectedMulTest(unittest.TestCase): + def test_matches_independent_vector(self): + self.assertEqual(expected_mul(MUL_A, MUL_B), MUL_EXPECTED) + + def test_multiplication_by_one_is_identity(self): + one = bytes([1]) + bytes(15) + self.assertEqual(expected_mul(MUL_A, one), MUL_A) + + def test_is_commutative(self): + self.assertEqual(expected_mul(MUL_A, MUL_B), expected_mul(MUL_B, MUL_A)) + + def test_rejects_wrong_operand_length(self): + with self.assertRaises(ValueError): + expected_mul(MUL_A[:15], MUL_B) + + +class DrainTest(unittest.TestCase): + def test_idle_port_is_polled_without_a_blocking_read(self): + with mock.patch.object(ulx3s_uart.time, "sleep"), mock.patch.object( + ulx3s_uart.time, "monotonic", side_effect=[0.0, 0.01, 0.06] + ): + self.assertEqual(ulx3s_uart.drain(IdleSerial()), b"") + + def test_available_byte_read_is_bounded_by_settle_deadline(self): + class StaleCountSerial: + timeout = 2.0 + in_waiting = 1 + + def read(self, _n: int = 1) -> bytes: + self.observed_timeout = self.timeout + return b"" + + fake = StaleCountSerial() + with mock.patch.object( + ulx3s_uart.time, "monotonic", side_effect=[10.0, 10.0, 10.051] + ): + self.assertEqual(ulx3s_uart.drain(fake, settle=0.05), b"") + self.assertGreater(fake.observed_timeout, 0) + self.assertAlmostEqual(fake.observed_timeout, 0.05) + self.assertEqual(fake.timeout, 2.0) + + def test_blocking_read_cannot_outlast_drain_deadline(self): + class StalledRead: + timeout = 1.0 + in_waiting = 1 + + def read(self, _n: int = 1) -> bytes: + threading.Event().wait(1.0) + return b"" + + start = time.monotonic() + with self.assertRaisesRegex(TimeoutError, "while reading"): + ulx3s_uart.drain(StalledRead(), settle=0.05) + self.assertLess(time.monotonic() - start, 0.3) + + def test_blocking_in_waiting_cannot_outlast_drain_deadline(self): + """Mutation-sensitive: direct ``ser.in_waiting`` would wait 30 seconds.""" + release = threading.Event() + self.addCleanup(release.set) + + class StalledQuery: + @property + def in_waiting(self) -> int: + release.wait(30) + return 0 + + start = time.monotonic() + with self.assertRaisesRegex(TimeoutError, "in_waiting"): + ulx3s_uart.drain(StalledQuery(), settle=0.05) + self.assertLess(time.monotonic() - start, 1.0) + + +class FlushDeadlineTest(unittest.TestCase): + """A stalled output drain must not outlive the transaction timeout.""" + + def test_stalled_flush_is_abandoned_at_the_transaction_deadline(self): + release = threading.Event() + self.addCleanup(release.set) + + class StalledFlush: + def write(self, data: bytes) -> int: + return len(data) + + def flush(self) -> None: + release.wait(30) + + start = time.monotonic() + with self.assertRaisesRegex(TimeoutError, "flush timeout"): + ulx3s_uart.send_bytes(StalledFlush(), b"\\x7e", timeout=0.05) + self.assertLess( + time.monotonic() - start, + 1.0, + "a blocked Serial.flush() outlived the transaction deadline", + ) + + def test_flush_receives_only_time_left_after_writes(self): + class Port: + def write(self, data: bytes) -> int: + return len(data) + + def flush(self) -> None: + pass + + # Model 60 ms of writes before the drain. A direct ``ser.flush()`` + # (or a fresh 80 ms worker budget) would bypass this assertion. + port = Port() + with mock.patch.object( + ulx3s_uart.time, "monotonic", side_effect=[10.0, 10.0, 10.06] + ), mock.patch.object( + ulx3s_uart, "_call_within", wraps=ulx3s_uart._call_within + ) as bounded: + ulx3s_uart.send_bytes(port, b"\x01\x02", timeout=0.08) + self.assertEqual(bounded.call_args.args[0], port.flush) + self.assertAlmostEqual(bounded.call_args.args[1], 0.02, places=9) + + def test_slow_writes_share_one_transaction_deadline(self): + """Mutation-sensitive: direct writes would allow one timeout per byte.""" + release = threading.Event() + self.addCleanup(release.set) + + class SlowPort: + write_timeout = 30.0 + + def write(self, data: bytes) -> int: + release.wait(30) + return len(data) + + def flush(self) -> None: + raise AssertionError("flush must not follow a timed-out write") + + start = time.monotonic() + with self.assertRaisesRegex(TimeoutError, "write timeout"): + ulx3s_uart.send_bytes(SlowPort(), b"\x01\x02\x03", timeout=0.05) + self.assertLess(time.monotonic() - start, 1.0) + + def test_partial_writes_rearm_only_the_remaining_deadline(self): + class PartialPort: + def __init__(self) -> None: + self.write_timeout = 30.0 + self.calls: list[tuple[bytes, float]] = [] + self.sent = bytearray() + + def write(self, data: bytes) -> int: + self.calls.append((data, self.write_timeout)) + self.sent.extend(data[:1]) + return 1 + + def flush(self) -> None: + pass + + port = PartialPort() + times = iter([10.0, 10.0, 10.02, 10.04, 10.06]) + with mock.patch.object(ulx3s_uart.time, "monotonic", side_effect=times): + ulx3s_uart.send_bytes(port, b"\x10\x20\x30", timeout=0.08) + self.assertEqual(bytes(port.sent), b"\x10\x20\x30") + self.assertEqual( + [data for data, _ in port.calls], + [b"\x10\x20\x30", b"\x20\x30", b"\x30"], + ) + self.assertEqual(port.write_timeout, 30.0) + for observed, expected in zip( + [budget for _, budget in port.calls], [0.08, 0.06, 0.04] + ): + self.assertAlmostEqual(observed, expected) + + def test_inter_byte_delay_uses_one_write_per_byte(self): + class FullBufferPort: + def __init__(self) -> None: + self.calls: list[bytes] = [] + + def write(self, data: bytes) -> int: + self.calls.append(data) + return len(data) + + def flush(self) -> None: + pass + + port = FullBufferPort() + with mock.patch.object(ulx3s_uart.time, "sleep") as sleep: + ulx3s_uart.send_bytes(port, b"\x10\x20\x30", inter_byte_delay=0.01) + self.assertEqual(port.calls, [b"\x10", b"\x20", b"\x30"]) + self.assertEqual(sleep.call_count, 2) + + +class MulExitStatusTest(unittest.TestCase): + def test_correct_product_succeeds(self): + self.assertEqual(run_mul(MUL_EXPECTED), 0) + + def test_single_flipped_bit_is_rejected(self): + wrong = bytearray(MUL_EXPECTED) + wrong[0] ^= 0x01 + self.assertEqual(len(wrong), 16) + self.assertEqual(run_mul(bytes(wrong)), 1) + + def test_flipped_bit_in_last_byte_is_rejected(self): + wrong = bytearray(MUL_EXPECTED) + wrong[15] ^= 0x80 + self.assertEqual(run_mul(bytes(wrong)), 1) + + def test_all_zero_response_is_rejected(self): + self.assertEqual(run_mul(bytes(16)), 1) + + def test_operands_echoed_back_are_rejected(self): + # A bridge that loops input to output returns a plausible 16 bytes. + self.assertEqual(run_mul(MUL_A), 1) + + def test_driver_sends_the_documented_command_framing(self): + fake = FakeSerial(MUL_EXPECTED, command_len=1 + 1 + 32) + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake): + ulx3s_uart.main( + ["--port", "/dev/null", "--tx", "mul", "--payload", (MUL_A + MUL_B).hex()] + ) + self.assertEqual( + fake.written, + bytes([ulx3s_uart.ABORT, ulx3s_uart.MUL128]) + MUL_A + MUL_B, + ) + + def test_cli_timeout_reaches_the_response_deadline(self): + fake = FakeSerial(MUL_EXPECTED, command_len=1 + 1 + 32) + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake), mock.patch.object( + ulx3s_uart, "recv_response", return_value=MUL_EXPECTED + ) as recv: + rc = ulx3s_uart.main( + [ + "--port", + "/dev/null", + "--tx", + "mul", + "--timeout", + "0.125", + "--payload", + (MUL_A + MUL_B).hex(), + ] + ) + self.assertEqual(rc, 0) + recv.assert_called_once_with(fake, 16, timeout=0.125) + + +class StatusSignatureTest(unittest.TestCase): + """`--tx status` is the default command, so an unchecked reply is the widest hole.""" + + def test_signature_matches_the_rtl_status_bytes(self): + # Parse status_byte()'s case arms so the host constant cannot drift from RTL. + body = _STREAM_ALU.read_text().split("function automatic [7:0] status_byte;")[1] + body = body.split("endfunction")[0] + arms = dict( + (int(i), int(v, 16)) + for i, v in re.findall(r"4'd(\d):\s*status_byte\s*=\s*8'h([0-9a-fA-F]{2});", body) + ) + rtl = bytes(arms[i] for i in range(4)) + self.assertEqual(rtl, ulx3s_uart.STATUS_SIGNATURE) + + def test_documented_signature_succeeds(self): + self.assertEqual(run_status(ulx3s_uart.STATUS_SIGNATURE), 0) + + def test_four_garbage_bytes_are_rejected(self): + self.assertEqual(run_status(bytes.fromhex("deadbeef")), 1) + + def test_all_zero_response_is_rejected(self): + self.assertEqual(run_status(bytes(4)), 1) + + def test_idle_line_pulled_high_is_rejected(self): + self.assertEqual(run_status(b"\xff" * 4), 1) + + def test_single_flipped_bit_is_rejected(self): + wrong = bytearray(ulx3s_uart.STATUS_SIGNATURE) + wrong[2] ^= 0x01 + self.assertEqual(run_status(bytes(wrong)), 1) + + def test_byte_swapped_signature_is_rejected(self): + self.assertEqual(run_status(ulx3s_uart.STATUS_SIGNATURE[::-1]), 1) + + def test_error_response_is_rejected(self): + # S_ERROR_TX emits 0xe0 for an unknown opcode; a bridge that mis-decodes + # STATUS must not look healthy. + self.assertEqual(run_status(b"\xe0" * 4), 1) + + def test_driver_sends_the_documented_command_framing(self): + fake = FakeSerial(ulx3s_uart.STATUS_SIGNATURE, command_len=2) + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake): + ulx3s_uart.main(["--port", "/dev/null", "--tx", "status"]) + self.assertEqual(fake.written, bytes([ulx3s_uart.ABORT, ulx3s_uart.STATUS])) + + def test_short_reply_is_not_silently_accepted(self): + with mock.patch("sys.stderr") as stderr: + self.assertEqual(run_status(ulx3s_uart.STATUS_SIGNATURE[:3]), 2) + self.assertIn("expected 4 bytes, got 3", str(stderr.write.call_args_list)) + + def test_serial_transport_failure_is_reported_as_communication_error(self): + # CI installs requirements.txt before this board-free suite. Do not + # allow the deferred import to hide a missing runtime dependency. + self.assertIsNotNone( + ulx3s_uart.serial, "pyserial must be installed from requirements.txt" + ) + fake = FakeSerial(b"", command_len=2) + with mock.patch.object( + ulx3s_uart, "open_port", return_value=fake + ), mock.patch.object( + ulx3s_uart, + "tx_status", + side_effect=ulx3s_uart.serial.SerialTimeoutException("write timed out"), + ), mock.patch("sys.stderr") as stderr: + rc = ulx3s_uart.main(["--port", "/dev/null", "--tx", "status"]) + self.assertEqual(rc, 2) + self.assertIn("write timed out", str(stderr.write.call_args_list)) + self.assertTrue(fake.closed) + + +class _FakeClock: + """Virtual clock, so deadline behaviour is asserted without real waiting.""" + + def __init__(self, start: float = 1000.0) -> None: + self.t = start + + def __call__(self) -> float: + return self.t + + def advance(self, seconds: float) -> None: + self.t += seconds + + +class _StallingPort: + """Delivers one byte late, then stalls for whatever timeout it was armed with.""" + + def __init__(self, clock, first_byte_after: float, port_timeout: float) -> None: + self.timeout = port_timeout + self._clock = clock + self._first_byte_after = first_byte_after + self.armed: list = [] + self.calls = 0 + + def read(self, n: int) -> bytes: + self.calls += 1 + self.armed.append(self.timeout) + if self.calls == 1: + self._clock.advance(self._first_byte_after) + return b"\x01" + # A real blocking read consumes exactly the timeout it was armed with. + self._clock.advance(self.timeout) + return b"" + + +class RecvExactDeadlineTest(unittest.TestCase): + """`recv_exact` must bound the whole call, not each read separately. + + pyserial applies the timeout set in open_port to every individual read, so + a byte arriving just before the deadline used to buy the read after it a + whole fresh timeout: a 2 s budget took 3.9 s. Re-arm from the time left. + """ + + def _run(self, budget=2.0, first_byte_after=1.9): + clock = _FakeClock() + port = _StallingPort(clock, first_byte_after, port_timeout=budget) + start = clock.t + with mock.patch.object(ulx3s_uart.time, "monotonic", clock), mock.patch.object( + ulx3s_uart.time, "sleep", lambda s: None + ): + with self.assertRaises(TimeoutError): + ulx3s_uart.recv_exact(port, 4, timeout=budget) + return port, clock.t - start + + def test_call_does_not_outlive_its_budget(self): + _, elapsed = self._run(budget=2.0, first_byte_after=1.9) + self.assertLessEqual(elapsed, 2.0 + 1e-9, "a late byte bought a second full timeout") + + def test_each_read_is_armed_with_only_the_time_left(self): + port, _ = self._run(budget=2.0, first_byte_after=1.9) + self.assertGreaterEqual(port.calls, 2) + self.assertAlmostEqual(port.armed[1], 0.1, places=9) + + def test_armed_timeouts_never_increase(self): + port, _ = self._run(budget=2.0, first_byte_after=0.5) + self.assertEqual(port.armed, sorted(port.armed, reverse=True)) + + def test_port_timeout_is_restored_for_the_next_transaction(self): + port, _ = self._run(budget=2.0, first_byte_after=1.9) + self.assertEqual(port.timeout, 2.0) + + def test_a_port_without_a_timeout_attribute_still_works(self): + # Re-arming must not require the object to already expose .timeout. + class Bare: + def __init__(self, data): + self.data = bytearray(data) + + def read(self, n): + chunk = bytes(self.data[:n]) + del self.data[:n] + return chunk + + self.assertEqual( + ulx3s_uart.recv_exact(Bare(ulx3s_uart.STATUS_SIGNATURE), 4, timeout=1.0), + ulx3s_uart.STATUS_SIGNATURE, + ) + + def test_blocking_read_cannot_outlast_response_deadline(self): + class StalledRead: + timeout = 1.0 + + def read(self, _n: int) -> bytes: + threading.Event().wait(1.0) + return b"" + + start = time.monotonic() + with self.assertRaisesRegex(TimeoutError, "response read deadline"): + ulx3s_uart.recv_exact(StalledRead(), 1, timeout=0.05) + self.assertLess(time.monotonic() - start, 0.3) + + +class AbortByteInPayloadTest(unittest.TestCase): + """0x7f inside an operand aborts the transaction in the bridge. + + uart_bridge.sv derives its abort pulse from any received 0x7f, so an + operand containing that byte is torn down mid-flight and the core replies + 0xe0. Confirmed in simulation: a SET128 whose payload byte 5 is 0x7f comes + back as 15 bytes with 0xe0 from byte 5 onward. Until the bridge framing + distinguishes payload from command, the host must refuse such an operand + rather than print MATCH: False and let a reader blame the silicon. + """ + + def test_set_payload_carrying_the_abort_byte_is_refused(self): + with self.assertRaises(ValueError) as ctx: + ulx3s_uart.tx_set(object(), bytes([0x7F]) + bytes(15)) + self.assertIn("7f", str(ctx.exception)) + + def test_offsets_of_every_abort_byte_are_reported(self): + payload = bytearray(16) + payload[3] = ulx3s_uart.ABORT + payload[11] = ulx3s_uart.ABORT + with self.assertRaises(ValueError) as ctx: + ulx3s_uart.reject_abort_byte("operand", bytes(payload)) + self.assertIn("3", str(ctx.exception)) + self.assertIn("11", str(ctx.exception)) + + def test_either_mul_operand_is_checked(self): + clean, dirty = bytes(16), bytes([ulx3s_uart.ABORT]) + bytes(15) + for a, b in ((dirty, clean), (clean, dirty)): + with self.subTest(a=a[:1], b=b[:1]): + with self.assertRaises(ValueError): + ulx3s_uart.tx_mul(object(), a, b) + + def test_either_xor_operand_is_checked(self): + clean, dirty = bytes(16), bytes(15) + bytes([ulx3s_uart.ABORT]) + for a, b in ((dirty, clean), (clean, dirty)): + with self.subTest(a=a[-1:], b=b[-1:]): + with self.assertRaises(ValueError): + ulx3s_uart.tx_xor(object(), a, b) + + def test_operands_without_the_abort_byte_are_untouched(self): + # The guard must not fire on the vectors the bench and CI already use. + ulx3s_uart.reject_abort_byte("a", MUL_A) + ulx3s_uart.reject_abort_byte("b", MUL_B) + ulx3s_uart.reject_abort_byte("expected", MUL_EXPECTED) + + def test_cli_exits_two_not_one_for_an_uncarryable_payload(self): + # Exit 1 means "the board answered wrong". This is not that, and a CI + # log that conflates them sends someone hunting a hardware fault. + payload = (bytes([ulx3s_uart.ABORT]) + bytes(15) + bytes(16)).hex() + fake = FakeSerial(b"", command_len=99) + with mock.patch.object(ulx3s_uart, "open_port", return_value=fake): + rc = ulx3s_uart.main(["--port", "/dev/null", "--tx", "mul", "--payload", payload]) + self.assertEqual(rc, 2) + self.assertEqual(fake.written, b"", "no bytes may reach the link") + + +class SurplusResponseByteTest(unittest.TestCase): + """A reply that merely *starts* correctly is not a correct reply. + + `recv_exact` returns the instant the nth byte lands, so a duplicated or + spurious trailing byte used to stay queued while the driver compared only + the prefix and exited 0 -- a bridge stuttering an extra byte read as a + clean pass. The link must be settled and found silent before a match is + reported. + """ + + def test_status_prefix_followed_by_a_surplus_byte_is_rejected(self): + self.assertNotEqual(run_status(ulx3s_uart.STATUS_SIGNATURE + b"\x00"), 0) + + def test_duplicated_status_reply_is_rejected(self): + self.assertNotEqual(run_status(ulx3s_uart.STATUS_SIGNATURE * 2), 0) + + def test_surplus_is_a_transport_fault_not_a_wrong_answer(self): + # Exit 1 means "the board answered wrong". A stuttering link is not + # that, and conflating them sends someone hunting a datapath bug. + with mock.patch("sys.stderr") as stderr: + self.assertEqual(run_status(ulx3s_uart.STATUS_SIGNATURE + b"\x00"), 2) + self.assertIn("surplus", str(stderr.write.call_args_list)) + + def test_mul_result_followed_by_an_error_byte_is_rejected(self): + self.assertNotEqual(run_mul(MUL_EXPECTED + b"\xe0"), 0) + + def test_mul_result_followed_by_a_surplus_byte_exits_two(self): + self.assertEqual(run_mul(MUL_EXPECTED + b"\x00"), 2) + + def test_exact_length_replies_still_pass(self): + # The guard must not fire on the clean case it is wrapped around. + self.assertEqual(run_status(ulx3s_uart.STATUS_SIGNATURE), 0) + self.assertEqual(run_mul(MUL_EXPECTED), 0) + + def test_surplus_bytes_are_named_in_the_message(self): + fake = FakeSerial(b"", command_len=0) + fake._pending.extend(ulx3s_uart.STATUS_SIGNATURE + b"\xab\xcd") + with self.assertRaises(ValueError) as ctx: + ulx3s_uart.recv_response(fake, 4) + self.assertIn("abcd", str(ctx.exception)) + + def test_every_command_path_uses_the_settling_reader(self): + # A new command that reaches for recv_exact directly would silently + # reopen the hole, so pin the seam rather than the four call sites. + source = Path(ulx3s_uart.__file__).read_text() + body = source.split("# MinCore constants for independent oracle")[1] + self.assertNotIn("recv_exact(", body, "a command bypasses recv_response") + self.assertIn("recv_response(", body) + + +class RecvResponseTest(unittest.TestCase): + def test_returns_the_response_when_the_link_is_silent(self): + fake = FakeSerial(b"", command_len=0) + fake._pending.extend(ulx3s_uart.STATUS_SIGNATURE) + self.assertEqual( + ulx3s_uart.recv_response(fake, 4), ulx3s_uart.STATUS_SIGNATURE + ) + + def test_raises_when_anything_follows_the_response(self): + fake = FakeSerial(b"", command_len=0) + fake._pending.extend(ulx3s_uart.STATUS_SIGNATURE + b"\x99") + with self.assertRaises(ValueError): + ulx3s_uart.recv_response(fake, 4) + + def test_settle_window_outlasts_a_byte_at_the_configured_baud(self): + # 10 bit times at BAUD is how long a straggler needs to land; a settle + # window shorter than that would race the byte it exists to catch. + self.assertGreater(ulx3s_uart.SETTLE_S, 10.0 / ulx3s_uart.BAUD) + + +_DOC = ( + Path(__file__).resolve().parent.parent / "docs" / "ULX3S_SMOKE_AND_UART.md" +) +_INVOCATION = "python3 -m fpga_harness.ulx3s_uart" + + +def _documented_invocations(): + """Every advertised command line, as (source, argv-after-the-module-name).""" + sources = [("ulx3s_uart docstring", ulx3s_uart.__doc__), (_DOC.name, _DOC.read_text())] + for origin, text in sources: + for raw in text.splitlines(): + line = raw.strip().lstrip("$ ").strip() + if not line.startswith(_INVOCATION): + continue + yield origin, line, shlex.split(line)[3:] + + +class DocumentedUsageTest(unittest.TestCase): + """A copy-pasteable example that argparse rejects is a broken example. + + The shipped usage line said `--tx 03` -- the opcode byte rather than the + command name -- so the one command a new user runs first exited 2 before + ever opening the port. + """ + + def test_examples_are_actually_found(self): + # Guards the parser below from passing vacuously if the docs are reshaped. + found = list(_documented_invocations()) + self.assertGreaterEqual(len(found), 3, f"only found: {found}") + + def test_every_documented_command_line_parses(self): + parser = ulx3s_uart.build_parser() + for origin, line, argv in _documented_invocations(): + with self.subTest(source=origin, line=line): + # parse_args calls sys.exit on a bad option instead of raising. + try: + parser.parse_args(argv) + except SystemExit as exc: + self.fail(f"{origin} advertises a command argparse rejects: {line} ({exc})") + + def test_every_documented_payload_has_the_right_width(self): + parser = ulx3s_uart.build_parser() + for origin, line, argv in _documented_invocations(): + with self.subTest(source=origin, line=line): + args = parser.parse_args(argv) + want = ulx3s_uart.PAYLOAD_BYTES[args.tx] + payload = bytes.fromhex(args.payload) if args.payload else b"" + self.assertEqual( + len(payload), want, f"{origin}: {args.tx} needs {want} payload bytes" + ) + + def test_opcode_byte_is_not_accepted_as_a_command_name(self): + # The exact regression: `--tx 03` must stay rejected, and must not be + # silently coerced into SET128 either. + for opcode in ("03", "0x03", str(ulx3s_uart.SET128)): + with self.subTest(opcode=opcode): + with self.assertRaises(SystemExit): + ulx3s_uart.build_parser().parse_args( + ["--port", "/dev/null", "--tx", opcode] + ) + + def test_parser_choices_cover_every_payload_width_entry(self): + parser = ulx3s_uart.build_parser() + choices = next(a.choices for a in parser._actions if a.dest == "tx") + self.assertEqual(set(choices), set(ulx3s_uart.PAYLOAD_BYTES)) + + def test_documented_runtime_dependency_is_pinned(self): + requirements = (Path(__file__).resolve().parent.parent / "requirements.txt").read_text() + self.assertRegex(requirements, r"(?m)^pyserial==3\.5$") + + +class TimeoutValidationTest(unittest.TestCase): + """Adversarial tests for non-finite / invalid timeout rejection. + + These must raise ValueError with a clear message for math.inf, NaN, + negative, zero, and values beyond ``threading.TIMEOUT_MAX``. + Tests are written to fail on pre-fix code (no explicit validation) + and pass after _validate_timeout is wired into the public entry points. + """ + + BAD_VALUES = [math.inf, float("nan"), -1.0, -0.0, 0.0] + SAFE_LARGE = 3600.0 # large finite that will not overflow platform time_t in worker.join + TOO_LARGE = threading.TIMEOUT_MAX * 2 + + def test_open_port_rejects_non_finite_and_non_positive(self): + for bad in self.BAD_VALUES: + with self.subTest(timeout=bad): + with self.assertRaisesRegex(ValueError, r"(finite|positive)"): + ulx3s_uart.open_port("/dev/null", timeout=bad) + + def test_rejects_timeouts_that_exceed_thread_join_range(self): + for entrypoint, args in ( + (ulx3s_uart.open_port, ("/dev/null",)), + (ulx3s_uart.recv_exact, (FakeSerial(b"", command_len=0), 1)), + (ulx3s_uart.send_bytes, (object(), b"\\x00")), + ): + with self.subTest(entrypoint=entrypoint.__name__): + with self.assertRaisesRegex(ValueError, "TIMEOUT_MAX"): + entrypoint(*args, timeout=self.TOO_LARGE) + with self.assertRaisesRegex(ValueError, "TIMEOUT_MAX"): + ulx3s_uart.drain(IdleSerial(), settle=self.TOO_LARGE) + + def test_open_port_accepts_very_large_finite(self): + # Should not raise from validation; FakeSerial is not used here, + # open_port will fail later on real serial but validation must pass. + try: + # We expect it to fail at serial creation (no pyserial or no port), + # not at our validation. + ulx3s_uart.open_port("/dev/null", timeout=self.SAFE_LARGE) + except RuntimeError as e: + # Expected when pyserial missing or port absent. + self.assertIn("pyserial", str(e)) + except Exception as e: + # Any other failure must not be a ValueError from validation. + self.assertNotIsInstance(e, ValueError) + + def test_recv_exact_rejects_non_finite_and_non_positive(self): + fake = FakeSerial(b"", command_len=0) + for bad in self.BAD_VALUES: + with self.subTest(timeout=bad): + with self.assertRaisesRegex(ValueError, r"(finite|positive)"): + ulx3s_uart.recv_exact(fake, 4, timeout=bad) + + def test_recv_exact_accepts_very_large_finite(self): + fake = FakeSerial(ulx3s_uart.STATUS_SIGNATURE, command_len=0) + fake._pending.extend(ulx3s_uart.STATUS_SIGNATURE) + # Must not raise ValueError; should succeed or raise Timeout only. + try: + out = ulx3s_uart.recv_exact(fake, 4, timeout=self.SAFE_LARGE) + self.assertEqual(out, ulx3s_uart.STATUS_SIGNATURE) + except TimeoutError: + pass + + def test_drain_rejects_non_finite_and_non_positive_settle(self): + for bad in self.BAD_VALUES: + with self.subTest(settle=bad): + with self.assertRaisesRegex(ValueError, r"(finite|positive)"): + ulx3s_uart.drain(IdleSerial(), settle=bad) + + def test_drain_accepts_very_large_finite_settle(self): + # Avoid worker.join(large) by patching the in_waiting helper. + # Use a clock that reports start then immediately "settled". + with mock.patch.object(ulx3s_uart, "_in_waiting_within", return_value=0): + with mock.patch.object( + ulx3s_uart.time, "monotonic", side_effect=[0.0, 0.0, self.SAFE_LARGE] + ): + with mock.patch.object(ulx3s_uart.time, "sleep"): + out = ulx3s_uart.drain(IdleSerial(), settle=self.SAFE_LARGE) + self.assertEqual(out, b"") + + def test_send_bytes_rejects_non_finite_timeout(self): + class DummyPort: + def write(self, data: bytes) -> int: + return len(data) + + def flush(self) -> None: + pass + + for bad in self.BAD_VALUES: + with self.subTest(timeout=bad): + with self.assertRaisesRegex(ValueError, r"(finite|positive)"): + ulx3s_uart.send_bytes(DummyPort(), b"\x00", timeout=bad) + + def test_main_cli_rejects_non_finite_timeout(self): + for bad in self.BAD_VALUES: + with self.subTest(timeout=bad): + rc = ulx3s_uart.main( + ["--port", "/dev/null", "--tx", "status", "--timeout", str(bad)] + ) + self.assertEqual(rc, 2) + + def test_main_cli_accepts_very_large_finite_timeout(self): + # CLI must accept the value; it will fail later opening the port. + rc = ulx3s_uart.main( + ["--port", "/dev/null", "--tx", "status", "--timeout", str(self.SAFE_LARGE)] + ) + # Expect 2 (cannot open) not 0/1 (success paths). + self.assertEqual(rc, 2) + + +if __name__ == "__main__": + unittest.main() diff --git a/fpga_harness/ulx3s_uart.py b/fpga_harness/ulx3s_uart.py new file mode 100644 index 0000000..f5379ad --- /dev/null +++ b/fpga_harness/ulx3s_uart.py @@ -0,0 +1,509 @@ +#!/usr/bin/env python3 +""" +ULX3S UART harness driver (NEW path under fpga_harness/). + +Explicit serial path only. No enumeration, no persistence, no auto-detect. +Opens a provided device path (e.g. /dev/ttyUSB0 or /dev/cu.usbserial-*) at 1 Mbaud 8N1. + +Protocol: exact lean_silicon_lsc1 / MinCore byte stream: + 0x03 SET128 : 16 bytes payload -> 16 bytes echo + 0x01 XOR128 : 32 bytes (A,B interleaved) -> 16 bytes + 0x02 MUL128 : 32 bytes (A then B) -> 16 bytes + +Every byte crosses the 8-bit ready/valid boundary. This driver only speaks bytes. + +Usage (explicit path). --tx takes the command name, not the opcode byte: + python3 -m fpga_harness.ulx3s_uart --port /dev/ttyUSB0 --tx status + python3 -m fpga_harness.ulx3s_uart --port /dev/ttyUSB0 --tx set --payload 000102030405060708090a0b0c0d0e0f +""" +from __future__ import annotations + +import argparse +import math +import sys +import threading +import time +from pathlib import Path +from typing import Optional + +# Deferred so the response-checking logic below can be imported and unit-tested +# on a machine with no pyserial and no board attached. +try: + import serial # pyserial +except ImportError: # pragma: no cover - only hit without pyserial installed + serial = None # type: ignore[assignment] + +COMMUNICATION_ERRORS = ( + (TimeoutError, serial.SerialException) if serial is not None else (TimeoutError,) +) + +# The GF(2^128) oracle lives in sim/, one level up from this package. +_REPO_ROOT = Path(__file__).resolve().parent.parent +if str(_REPO_ROOT) not in sys.path: + sys.path.insert(0, str(_REPO_ROOT)) + +from sim.model import ( # noqa: E402 + gf_mul_bitserial, + gf_mul_polynomial, + int_to_le_bytes, + le_bytes_to_int, +) + +BAUD = 1_000_000 +TIMEOUT_S = 2.0 + + +def _validate_timeout(timeout: float, name: str = "timeout") -> None: + """Reject non-finite and non-positive timeouts before any deadline arithmetic. + + math.inf and float('nan') produce no finite bound and can raise OverflowError + when assigned to pyserial timeouts or passed to worker.join(). Negative or + zero values produce an already-expired deadline. + """ + if not math.isfinite(timeout): + raise ValueError(f"{name} must be a finite number of seconds, got {timeout!r}") + if timeout <= 0: + raise ValueError(f"{name} must be positive, got {timeout!r}") + if timeout > threading.TIMEOUT_MAX: + raise ValueError( + f"{name} must not exceed threading.TIMEOUT_MAX " + f"({threading.TIMEOUT_MAX!r} seconds)" + ) + + +def _call_within(call, remaining: float, timeout_message: str): + """Run one uninterruptible serial operation within the remaining deadline. + + pyserial exposes a few synchronous operations (notably ``flush``) that do + not accept a timeout. The MinCore transport handles those with a daemon + worker: when a backend wedges, the transaction fails on its deadline rather + than waiting forever. The worker cannot safely be killed, so callers must + abandon this serial object after a timeout (the CLI closes it in ``finally``) + and must never issue a later transaction through it. + """ + if remaining <= 0: + raise TimeoutError(timeout_message) + outcome: list[object] = [] + failures: list[BaseException] = [] + + def run() -> None: + try: + outcome.append(call()) + except BaseException as error: + failures.append(error) + + worker = threading.Thread(target=run, daemon=True) + worker.start() + worker.join(remaining) + if worker.is_alive(): + raise TimeoutError(timeout_message) + if failures: + raise failures[0] + return outcome[0] + + +def _in_waiting_within(ser: serial.Serial, remaining: float) -> int: + """Return ``in_waiting`` without letting its backend query outlive deadline. + + pyserial exposes this as a property, but a disconnecting/stalled backend can + still block while evaluating it. Run the query on a daemon worker, just as + the host MinCore transport bounds backend calls, so a stale-byte drain never + spends longer than its settling budget merely asking whether bytes exist. + """ + return max(0, int(_call_within( + lambda: ser.in_waiting, + remaining, + "stale-input drain deadline expired while querying in_waiting", + ))) + + +def open_port(path: str, baud: int = BAUD, timeout: float = TIMEOUT_S) -> serial.Serial: + """Open with explicit path. Caller owns lifetime.""" + _validate_timeout(timeout, "timeout") + if serial is None: + raise RuntimeError("pyserial is required to reach a board; pip install -r requirements.txt") + ser = serial.Serial( + port=path, + baudrate=baud, + bytesize=serial.EIGHTBITS, + parity=serial.PARITY_NONE, + stopbits=serial.STOPBITS_ONE, + timeout=timeout, + write_timeout=timeout, + rtscts=False, + dsrdtr=False, + xonxoff=False, + ) + try: + ser.setDTR(False) + ser.setRTS(False) + except Exception: + pass + ser.reset_input_buffer() + ser.reset_output_buffer() + time.sleep(0.05) + return ser + + +def drain(ser: serial.Serial, max_bytes: int = 256, settle: float = 0.05) -> bytes: + """Drain up to N stale bytes; used between transactions and after reset.""" + _validate_timeout(settle, "settle") + out = bytearray() + deadline = time.monotonic() + settle + restore = getattr(ser, "timeout", None) + try: + while len(out) < max_bytes: + remaining = deadline - time.monotonic() + if remaining <= 0: + break + waiting = _in_waiting_within(ser, remaining) + if not waiting: + time.sleep(min(0.001, remaining)) + continue + # in_waiting is only a snapshot. A disconnect or another reader can + # make the following read block despite the positive count, so bind + # that read to the drain operation's remaining settle budget. + if hasattr(ser, "timeout"): + ser.timeout = remaining + out.extend(_call_within( + lambda: ser.read(min(waiting, max_bytes - len(out))), + remaining, + "stale-input drain deadline expired while reading", + )) + finally: + if restore is not None: + ser.timeout = restore + return bytes(out) + + +def send_bytes( + ser: serial.Serial, + data: bytes, + inter_byte_delay: float = 0.0, + timeout: float = TIMEOUT_S, +) -> None: + """Write a request and bound every write and drain by one deadline. + + ``Serial.write`` may block up to ``write_timeout`` and is permitted to + return a short count. Neither is a reason to grant a fresh full timeout: + one request has one budget. Each backend call therefore receives only the + time left, is additionally bounded by a worker for implementations that + ignore ``write_timeout``, and advances only by bytes actually accepted. + """ + _validate_timeout(timeout, "timeout") + deadline = time.monotonic() + timeout + restore_write_timeout = getattr(ser, "write_timeout", None) + offset = 0 + try: + while offset < len(data): + remaining = deadline - time.monotonic() + if remaining <= 0: + raise TimeoutError("write timeout before the request was sent") + if hasattr(ser, "write_timeout"): + ser.write_timeout = remaining + chunk = data[offset : offset + 1] if inter_byte_delay > 0 else data[offset:] + written = _call_within( + lambda: ser.write(chunk), + remaining, + "write timeout before the request was sent", + ) + if ( + not isinstance(written, int) + or written < 0 + or written > len(chunk) + ): + raise OSError(f"serial write returned invalid byte count {written!r}") + if written == 0: + # A nonblocking backend can make no progress; avoid a hot spin + # while still charging this pause to the same transaction. + time.sleep(min(0.0005, max(0.0, deadline - time.monotonic()))) + continue + offset += written + if inter_byte_delay > 0 and offset < len(data): + remaining = deadline - time.monotonic() + if remaining <= 0: + raise TimeoutError("write timeout before the request was sent") + time.sleep(min(inter_byte_delay, remaining)) + _call_within( + ser.flush, + deadline - time.monotonic(), + "flush timeout before the request drained", + ) + finally: + if restore_write_timeout is not None: + ser.write_timeout = restore_write_timeout + + +def recv_exact(ser: serial.Serial, n: int, timeout: float = TIMEOUT_S) -> bytes: + """Read exactly n bytes or raise once `timeout` seconds have passed. + + The port's own timeout is re-armed to the time actually left before each + read. Leaving it at the value set in open_port bounds each read separately + rather than the call as a whole, so a byte landing just before the deadline + buys the read after it a whole fresh timeout: a 2 s budget takes nearly 4 s, + and a dribbling link stretches it further still. + """ + _validate_timeout(timeout, "timeout") + buf = bytearray() + deadline = time.monotonic() + timeout + restore = getattr(ser, "timeout", None) + try: + while len(buf) < n: + remaining = deadline - time.monotonic() + if remaining <= 0: + break + ser.timeout = remaining + chunk = _call_within( + lambda: ser.read(n - len(buf)), + remaining, + "response read deadline expired", + ) + if chunk: + buf.extend(chunk) + else: + time.sleep(max(0.0, min(0.0005, deadline - time.monotonic()))) + finally: + if restore is not None: + ser.timeout = restore + if len(buf) != n: + raise TimeoutError(f"expected {n} bytes, got {len(buf)}") + return bytes(buf) + + +# A byte at 1 Mbaud is 10 bit times, ~10 us. Waiting three orders of magnitude +# longer means a straggler already on the wire is observed rather than raced. +SETTLE_S = 0.01 + + +def recv_response(ser: serial.Serial, n: int, timeout: float = TIMEOUT_S) -> bytes: + """Read exactly n bytes, then require the link to fall silent. + + recv_exact returns the instant the nth byte lands, so a duplicated or + spurious trailing byte stays queued and the caller only ever compares the + prefix. A reply that is wrong but happens to start with the right n bytes + would then be reported as a match and exit 0, which is precisely the + outcome a hardware experiment must never produce. + """ + resp = recv_exact(ser, n, timeout=timeout) + surplus = drain(ser, settle=SETTLE_S) + if surplus: + raise ValueError( + f"link sent {len(surplus)} surplus byte(s) after the expected " + f"{n}-byte response: {surplus.hex()}" + ) + return resp + + +# MinCore constants for independent oracle +SET128 = 0x03 +XOR128 = 0x01 +MUL128 = 0x02 +CLEAR = 0x7d +STATUS = 0x7e +ABORT = 0x7f + +# Fixed reply of status_byte() in asic_core/rtl/leanvm_b_stream_alu.sv: +# protocol major, protocol minor, opcode bitmap (XOR|MUL|SET|NONZERO), lane width. +STATUS_SIGNATURE = bytes([0x01, 0x01, 0x0F, 0x08]) + + +def expected_mul(a: bytes, b: bytes) -> bytes: + """Expected GF(2^128) product of two little-endian 16-byte operands. + + Computed by both oracles in sim.model and cross-checked. They share no + intermediate steps: one is schoolbook carry-less multiply plus long + reduction, the other is the LSB-first bit-serial recurrence the RTL uses. + A disagreement means the oracle itself is broken, which must not be + reported as a board failure. + """ + if len(a) != 16 or len(b) != 16: + raise ValueError("operands must be 16 bytes each") + a_int = le_bytes_to_int(a) + b_int = le_bytes_to_int(b) + poly = gf_mul_polynomial(a_int, b_int) + bitserial = gf_mul_bitserial(a_int, b_int) + if poly != bitserial: + raise AssertionError( + f"GF(2^128) oracles disagree: {poly:032x} vs {bitserial:032x}" + ) + return int_to_le_bytes(poly, 16) + + +def resync(ser: serial.Serial, timeout: float = TIMEOUT_S) -> None: + """Abort any partial prior command before beginning a new transaction.""" + drain(ser) + send_bytes(ser, bytes([ABORT]), timeout=timeout) + + +def reject_abort_byte(label: str, data: bytes) -> None: + """Refuse operands the bridge cannot carry intact. + + fpga/ulx3s/uart_bridge.sv raises its abort pulse on *any* received 0x7f, + including one that lands inside an operand, so the transaction is torn down + mid-flight and the core answers 0xe0 for the remaining bytes. A 128-bit + operand is arbitrary data, so this is reachable by ordinary vectors. Failing + here keeps a transport limitation from being reported as a wrong product. + """ + offsets = [i for i, b in enumerate(data) if b == ABORT] + if offsets: + raise ValueError( + f"{label} contains the abort byte 0x{ABORT:02x} at offset(s) " + f"{', '.join(str(i) for i in offsets)}; the UART bridge treats it as " + f"an abort, so this operand cannot cross the link intact" + ) + + +def tx_set(ser: serial.Serial, value: bytes, timeout: float = TIMEOUT_S) -> bytes: + assert len(value) == 16 + reject_abort_byte("SET128 value", value) + resync(ser, timeout=timeout) + send_bytes(ser, bytes([SET128]) + value, timeout=timeout) + echo = recv_response(ser, 16, timeout=timeout) + return echo + + +def tx_xor( + ser: serial.Serial, a: bytes, b: bytes, timeout: float = TIMEOUT_S +) -> bytes: + assert len(a) == 16 and len(b) == 16 + reject_abort_byte("XOR128 operand A", a) + reject_abort_byte("XOR128 operand B", b) + resync(ser, timeout=timeout) + pkt = bytes([XOR128]) + for i in range(16): + pkt += bytes([a[i], b[i]]) + send_bytes(ser, pkt, timeout=timeout) + res = recv_response(ser, 16, timeout=timeout) + return res + + +def tx_mul( + ser: serial.Serial, a: bytes, b: bytes, timeout: float = TIMEOUT_S +) -> bytes: + assert len(a) == 16 and len(b) == 16 + reject_abort_byte("MUL128 operand A", a) + reject_abort_byte("MUL128 operand B", b) + resync(ser, timeout=timeout) + send_bytes(ser, bytes([MUL128]) + a + b, timeout=timeout) + res = recv_response(ser, 16, timeout=timeout) + return res + + +def tx_clear(ser: serial.Serial, timeout: float = TIMEOUT_S) -> None: + resync(ser, timeout=timeout) + send_bytes(ser, bytes([CLEAR]), timeout=timeout) + + +def tx_status(ser: serial.Serial, timeout: float = TIMEOUT_S) -> bytes: + resync(ser, timeout=timeout) + send_bytes(ser, bytes([STATUS]), timeout=timeout) + return recv_response(ser, 4, timeout=timeout) + + +# Payload width each command consumes, in bytes. Single source of truth for the +# CLI validation below and for the usage examples the docs advertise. +PAYLOAD_BYTES = {"set": 16, "xor": 32, "mul": 32, "status": 0, "clear": 0} + + +def build_parser() -> argparse.ArgumentParser: + ap = argparse.ArgumentParser(description="ULX3S UART driver for LSC-1 MinCore smoke") + ap.add_argument("--port", required=True, help="Explicit serial device, e.g. /dev/ttyUSB0 or /dev/cu.usbserial-XXXX") + ap.add_argument("--tx", choices=sorted(PAYLOAD_BYTES), default="status") + ap.add_argument("--payload", default="", help="hex payload (for set: 32 hex chars; xor/mul: 64 hex chars)") + ap.add_argument("--timeout", type=float, default=TIMEOUT_S) + return ap + + +def main(argv: Optional[list[str]] = None) -> int: + args = build_parser().parse_args(argv) + + try: + _validate_timeout(args.timeout, "timeout") + except ValueError as e: + print(f"ERROR: {e}", file=sys.stderr) + return 2 + + port_path = args.port + try: + ser = open_port(port_path, timeout=args.timeout) + except Exception as e: + print(f"ERROR: cannot open {port_path}: {e}", file=sys.stderr) + return 2 + + try: + stale = drain(ser) + if stale: + print(f"drained {len(stale)} stale bytes at open", file=sys.stderr) + + if args.tx == "clear": + tx_clear(ser, timeout=args.timeout) + print("CLEAR sent") + return 0 + + if args.tx == "status": + st = tx_status(ser, timeout=args.timeout) + print("STATUS:", st.hex()) + print("STATUS exp:", STATUS_SIGNATURE.hex()) + ok = st == STATUS_SIGNATURE + print("MATCH:", ok) + return 0 if ok else 1 + + if not args.payload: + print("ERROR: --payload required for set/xor/mul", file=sys.stderr) + return 2 + try: + pay = bytes.fromhex(args.payload) + except ValueError: + print("ERROR: payload must be hex", file=sys.stderr) + return 2 + + want = PAYLOAD_BYTES[args.tx] + if len(pay) != want: + print( + f"ERROR: {args.tx} expects {want} bytes ({want * 2} hex chars)", + file=sys.stderr, + ) + return 2 + + if args.tx == "set": + echo = tx_set(ser, pay, timeout=args.timeout) + print("SET echo:", echo.hex()) + ok = echo == pay + print("MATCH:", ok) + return 0 if ok else 1 + + if args.tx == "xor": + a, b = pay[:16], pay[16:] + res = tx_xor(ser, a, b, timeout=args.timeout) + exp = bytes(x ^ y for x, y in zip(a, b)) + print("XOR res :", res.hex()) + print("XOR exp :", exp.hex()) + print("MATCH:", res == exp) + return 0 if res == exp else 1 + + if args.tx == "mul": + a, b = pay[:16], pay[16:] + res = tx_mul(ser, a, b, timeout=args.timeout) + exp = expected_mul(a, b) + print("MUL res :", res.hex()) + print("MUL exp :", exp.hex()) + ok = res == exp + print("MATCH:", ok) + return 0 if ok else 1 + + return 0 + except (ValueError,) + COMMUNICATION_ERRORS as e: + # A payload the link cannot carry or a transaction that did not + # complete is not a bad board result, so neither may share exit 1 with + # a complete response that genuinely mismatches its oracle. + print(f"ERROR: {e}", file=sys.stderr) + return 2 + finally: + try: + ser.close() + except Exception: + pass + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/requirements.txt b/requirements.txt index 8392d54..ca53928 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1 +1,2 @@ PyYAML==6.0.2 +pyserial==3.5 diff --git a/results/ulx3s-smoke-uart-20260725/SHA256SUMS b/results/ulx3s-smoke-uart-20260725/SHA256SUMS new file mode 100644 index 0000000..4de0b7a --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/SHA256SUMS @@ -0,0 +1,3 @@ +96eb9eda7421bac902eacaeced21eee0db9a80b8f2f2effdb52b515d68e0b2e3 ulx3s_smoke.bit +8243770de3fb1cb65f8ef0ee345addab105cf7e219d0c3be5cf009743e27f59f smoke.config +0a2dcd734f194819b6483b6d5a7e394677eb30634760d46a62d4f5542cdec944 smoke.svf diff --git a/results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt b/results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt new file mode 100644 index 0000000..f0758de --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/SHA256SUMS_bridge.txt @@ -0,0 +1 @@ +eacee77bdca486f173cacdb56709e442942eb85f9111eabcb96026976f8bae51 ulx3s_bridge.bit diff --git a/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt b/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt new file mode 100644 index 0000000..d38d40f --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST.txt @@ -0,0 +1,9 @@ +=== SOURCE PROVENANCE === +revision: a11c521a0a09168ff91a0ffcf0aa3fd5787f8271 +inputs-match-revision: yes +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +2193c115f54fc49c77280a544b0963bbff3cc5840fb5795fdf44e7dcb44f5781 fpga/ulx3s/build_smoke.sh +cd4a528e8502a4761efa123743afd1f6e180681af3349f05c5777ee489a92689 fpga/ulx3s/smoke_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf diff --git a/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt b/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt new file mode 100644 index 0000000..f4f018e --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/SOURCE_MANIFEST_uart.txt @@ -0,0 +1,16 @@ +=== SOURCE PROVENANCE === +revision: a11c521a0a09168ff91a0ffcf0aa3fd5787f8271 +inputs-match-revision: yes +d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614 asic_core/rtl/gf128_mul_bitstream.sv +4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396 asic_core/rtl/gf2n_mul_bitstream.sv +bcbfdd0844fa786e637fdf1b973f30c94e7929b07020955ea89baf143bd9c671 asic_core/rtl/lean_silicon_lsc1.sv +bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b asic_core/rtl/leanvm_b_stream_alu.sv +737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326 tools/portable_build_support.py +e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a tools/atomic_publish.py +a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db tools/source_provenance.py +da9ff87e6546086c402879bb6b0f3c21f7df2712c70ad103872462369e222381 fpga/ulx3s/build_uart.sh +b2226a0db5c80da4de9ab630caf40f42678cb15acd3fa2f4f661f5d101146931 fpga/ulx3s/uart_bridge.sv +b51f1a3974e7ae32bcbf9c32716aa9eb7d205e46e158a3f535bac7c04a57f7de fpga/ulx3s/uart_rx.sv +27def7ca1fefd66a510371aa1e7be55a6671ad195a94c1215f962028de6adcc9 fpga/ulx3s/uart_tx.sv +76513d0e0245b1e212b71ad56fdafeaa0a9654535a665f977bee4ef41a5bbd8f fpga/ulx3s/ulx3s_top.sv +1b2982830abbaaf932c48f8df3d0163e450e9cab6d065998f25984b677d415f2 fpga/ulx3s/ulx3s_v318_smoke.lpf diff --git a/results/ulx3s-smoke-uart-20260725/nextpnr.log b/results/ulx3s-smoke-uart-20260725/nextpnr.log new file mode 100644 index 0000000..18a77af --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/nextpnr.log @@ -0,0 +1,303 @@ +Info: constraining clock net 'clk' to 25.00 MHz + +Info: Logic utilisation before packing: +Info: Total LUT4s: 28/83640 0% +Info: logic LUTs: 2/83640 0% +Info: carry LUTs: 26/83640 0% +Info: RAM LUTs: 0/10455 0% +Info: RAMW LUTs: 0/20910 0% + +Info: Total DFFs: 25/83640 0% + +Info: Packing IOs.. +Info: pin 'led$tr_io' constrained to Bel 'X0/Y35/PIOC'. +Info: pin 'clk$tr_io' constrained to Bel 'X0/Y47/PIOA'. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 25 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0xf9bca309 + +Info: Device utilisation: +Info: TRELLIS_IO: 2/ 365 0% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 208 0% +Info: MULT18X18D: 0/ 156 0% +Info: ALU54B: 0/ 78 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 224 0% +Info: SIOLOGIC: 0/ 141 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 14 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 25/ 83640 0% +Info: TRELLIS_COMB: 34/ 83640 0% +Info: TRELLIS_RAMW: 0/ 10455 0% + +Info: Placed 2 cells based on constraints. +Info: Creating initial analytic placement for 4 cells, random placement wirelen = 308. +Info: at initial placer iter 0, wirelen = 10 +Info: at initial placer iter 1, wirelen = 10 +Info: at initial placer iter 2, wirelen = 10 +Info: at initial placer iter 3, wirelen = 10 +Info: Running main analytical placer, max placement attempts per cell = 10000. +Info: at iteration #1, type TRELLIS_COMB: wirelen solved = 10, spread = 21, legal = 23; time = 0.02s +Info: at iteration #2, type TRELLIS_COMB: wirelen solved = 10, spread = 10, legal = 19; time = 0.00s +Info: at iteration #3, type TRELLIS_COMB: wirelen solved = 11, spread = 11, legal = 19; time = 0.00s +Info: at iteration #4, type TRELLIS_COMB: wirelen solved = 13, spread = 13, legal = 21; time = 0.00s +Info: at iteration #5, type TRELLIS_COMB: wirelen solved = 13, spread = 20, legal = 22; time = 0.00s +Info: at iteration #6, type TRELLIS_COMB: wirelen solved = 14, spread = 14, legal = 18; time = 0.00s +Info: at iteration #7, type TRELLIS_COMB: wirelen solved = 14, spread = 14, legal = 23; time = 0.00s +Info: at iteration #8, type TRELLIS_COMB: wirelen solved = 14, spread = 14, legal = 18; time = 0.00s +Info: at iteration #9, type TRELLIS_COMB: wirelen solved = 14, spread = 14, legal = 20; time = 0.00s +Info: at iteration #10, type TRELLIS_COMB: wirelen solved = 14, spread = 21, legal = 22; time = 0.00s +Info: at iteration #11, type TRELLIS_COMB: wirelen solved = 16, spread = 16, legal = 18; time = 0.00s +Info: HeAP Placer Time: 0.10s +Info: of which solving equations: 0.00s +Info: of which spreading cells: 0.02s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 1, wirelen = 18 +Info: at iteration #2: temp = 0.000000, timing cost = 1, wirelen = 18 +Info: SA placement time 0.00s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 352.61 MHz (PASS at 25.00 MHz) + +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.16 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 37164, 37268) |*** +Info: [ 37268, 37372) |*** +Info: [ 37372, 37476) |*** +Info: [ 37476, 37580) |*** +Info: [ 37580, 37684) |*** +Info: [ 37684, 37788) |*** +Info: [ 37788, 37892) |*** +Info: [ 37892, 37996) |*** +Info: [ 37996, 38100) | +Info: [ 38100, 38204) | +Info: [ 38204, 38308) | +Info: [ 38308, 38412) | +Info: [ 38412, 38516) | +Info: [ 38516, 38620) | +Info: [ 38620, 38724) | +Info: [ 38724, 38828) | +Info: [ 38828, 38932) | +Info: [ 38932, 39036) | +Info: [ 39036, 39140) | +Info: [ 39140, 39244) |* +Info: Checksum: 0x1494b81a +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 84 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 84 | 0 69 | 0 69 | 0| 0.01 0.01| +Info: Routing complete. +Info: Router1 time 0.01s +Info: Checksum: 0x2e9a1022 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source cnt_TRELLIS_FF_Q_10.Q +Info: routing 1.10 1.62 Net cnt[0] (2,30) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2$CCU2_COMB0.B +Info: Defined in: +Info: smoke_top.sv:12.16-12.19 +Info: logic 0.45 2.07 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2$CCU2_COMB0.FCO +Info: routing 0.00 2.07 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2$CCU2_FCI_INT (2,31) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2$CCU2_COMB1.FCI +Info: logic 0.00 2.07 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2$CCU2_COMB1.FCO +Info: routing 0.00 2.07 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_2_COUT (2,31) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.14 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6$CCU2_COMB0.FCO +Info: routing 0.00 2.14 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6$CCU2_FCI_INT (2,31) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6$CCU2_COMB1.FCI +Info: logic 0.00 2.14 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6$CCU2_COMB1.FCO +Info: routing 0.00 2.14 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_6_COUT (2,31) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.21 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7$CCU2_COMB0.FCO +Info: routing 0.00 2.21 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7$CCU2_FCI_INT (2,31) -> (2,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7$CCU2_COMB1.FCI +Info: logic 0.00 2.21 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7$CCU2_COMB1.FCO +Info: routing 0.00 2.21 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_7_COUT (2,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.28 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4$CCU2_COMB0.FCO +Info: routing 0.00 2.28 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4$CCU2_FCI_INT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4$CCU2_COMB1.FCI +Info: logic 0.00 2.28 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4$CCU2_COMB1.FCO +Info: routing 0.00 2.28 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_4_COUT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.36 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1$CCU2_COMB0.FCO +Info: routing 0.00 2.36 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1$CCU2_FCI_INT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1$CCU2_COMB1.FCI +Info: logic 0.00 2.36 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1$CCU2_COMB1.FCO +Info: routing 0.00 2.36 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_1_COUT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.43 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1$CCU2_COMB0.FCO +Info: routing 0.00 2.43 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1$CCU2_FCI_INT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1$CCU2_COMB1.FCI +Info: logic 0.00 2.43 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1$CCU2_COMB1.FCO +Info: routing 0.00 2.43 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_COUT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.50 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3$CCU2_COMB0.FCO +Info: routing 0.00 2.50 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3$CCU2_FCI_INT (3,31) -> (3,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3$CCU2_COMB1.FCI +Info: logic 0.00 2.50 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3$CCU2_COMB1.FCO +Info: routing 0.00 2.50 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_3_COUT (3,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.57 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9$CCU2_COMB0.FCO +Info: routing 0.00 2.57 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9$CCU2_FCI_INT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9$CCU2_COMB1.FCI +Info: logic 0.00 2.57 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9$CCU2_COMB1.FCO +Info: routing 0.00 2.57 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_9_COUT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.64 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8$CCU2_COMB0.FCO +Info: routing 0.00 2.64 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8$CCU2_FCI_INT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8$CCU2_COMB1.FCI +Info: logic 0.00 2.64 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8$CCU2_COMB1.FCO +Info: routing 0.00 2.64 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_8_COUT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.71 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11$CCU2_COMB0.FCO +Info: routing 0.00 2.71 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11$CCU2_FCI_INT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11$CCU2_COMB1.FCI +Info: logic 0.00 2.71 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11$CCU2_COMB1.FCO +Info: routing 0.00 2.71 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_11_COUT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.78 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5$CCU2_COMB0.FCO +Info: routing 0.00 2.78 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5$CCU2_FCI_INT (4,31) -> (4,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5$CCU2_COMB1.FCI +Info: logic 0.00 2.78 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5$CCU2_COMB1.FCO +Info: routing 0.00 2.78 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_5_COUT (4,31) -> (5,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.07 2.85 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10$CCU2_COMB0.FCO +Info: routing 0.00 2.85 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10$CCU2_FCI_INT (5,31) -> (5,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10$CCU2_COMB1.FCI +Info: logic 0.00 2.85 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10$CCU2_COMB1.FCO +Info: routing 0.00 2.85 Net cnt_TRELLIS_FF_Q_DI_CCU2C_S1_10_COUT (5,31) -> (5,31) +Info: Sink cnt_TRELLIS_FF_Q_DI_CCU2C_S0$CCU2_COMB0.FCI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.44 3.30 Source cnt_TRELLIS_FF_Q_DI_CCU2C_S0$CCU2_COMB0.F +Info: routing 0.13 3.42 Net cnt_TRELLIS_FF_Q_DI[24] (5,31) -> (5,31) +Info: Sink cnt_TRELLIS_FF_Q_23.DI +Info: Defined in: +Info: smoke_top.sv:14.16-14.26 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:34.26-34.27 +Info: setup 0.00 3.42 Source cnt_TRELLIS_FF_Q_23.DI +Info: 2.20 ns logic, 1.23 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source cnt_TRELLIS_FF_Q_23.Q +Info: routing 0.75 1.28 Net cnt[24] (5,31) -> (3,33) +Info: Sink led_LUT4_Z.D +Info: Defined in: +Info: smoke_top.sv:12.16-12.19 +Info: logic 0.24 1.51 Source led_LUT4_Z.F +Info: routing 1.38 2.89 Net led$TRELLIS_IO_OUT (3,33) -> (0,35) +Info: Sink led$tr_io.I +Info: Defined in: +Info: smoke_top.sv:9.17-9.20 +Info: 0.76 ns logic, 2.13 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 291.97 MHz (PASS at 25.00 MHz) + +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 2.89 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 36575, 36691) |**** +Info: [ 36691, 36807) |** +Info: [ 36807, 36923) |**** +Info: [ 36923, 37039) |*** +Info: [ 37039, 37155) |**** +Info: [ 37155, 37271) |*** +Info: [ 37271, 37387) |** +Info: [ 37387, 37503) |** +Info: [ 37503, 37619) | +Info: [ 37619, 37735) | +Info: [ 37735, 37851) | +Info: [ 37851, 37967) | +Info: [ 37967, 38083) | +Info: [ 38083, 38199) | +Info: [ 38199, 38315) | +Info: [ 38315, 38431) | +Info: [ 38431, 38547) | +Info: [ 38547, 38663) | +Info: [ 38663, 38779) | +Info: [ 38779, 38895) |* + +Info: Program finished normally. diff --git a/results/ulx3s-smoke-uart-20260725/nextpnr_uart.log b/results/ulx3s-smoke-uart-20260725/nextpnr_uart.log new file mode 100644 index 0000000..b8a56d2 --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/nextpnr_uart.log @@ -0,0 +1,236 @@ +Info: constraining clock net 'clk' to 25.00 MHz + +Info: Logic utilisation before packing: +Info: Total LUT4s: 681/83640 0% +Info: logic LUTs: 613/83640 0% +Info: carry LUTs: 68/83640 0% +Info: RAM LUTs: 0/10455 0% +Info: RAMW LUTs: 0/20910 0% + +Info: Total DFFs: 402/83640 0% + +Info: Packing IOs.. +Info: pin 'uart_tx$tr_io' constrained to Bel 'X0/Y56/PIOC'. +Info: pin 'uart_rx$tr_io' constrained to Bel 'X0/Y89/PIOB'. +Info: pin 'led$tr_io' constrained to Bel 'X0/Y35/PIOC'. +Info: pin 'clk$tr_io' constrained to Bel 'X0/Y47/PIOA'. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 360 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x3c53a585 + +Info: Device utilisation: +Info: TRELLIS_IO: 4/ 365 1% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 208 0% +Info: MULT18X18D: 0/ 156 0% +Info: ALU54B: 0/ 78 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 224 0% +Info: SIOLOGIC: 0/ 141 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 14 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 402/ 83640 0% +Info: TRELLIS_COMB: 703/ 83640 0% +Info: TRELLIS_RAMW: 0/ 10455 0% + +Info: Placed 4 cells based on constraints. +Info: Creating initial analytic placement for 632 cells, random placement wirelen = 71449. +Info: at initial placer iter 0, wirelen = 159 +Info: at initial placer iter 1, wirelen = 142 +Info: at initial placer iter 2, wirelen = 121 +Info: at initial placer iter 3, wirelen = 129 +Info: Running main analytical placer, max placement attempts per cell = 154012. +Info: at iteration #1, type ALL: wirelen solved = 119, spread = 2521, legal = 2638; time = 0.03s +Info: at iteration #2, type ALL: wirelen solved = 314, spread = 1942, legal = 2074; time = 0.02s +Info: at iteration #3, type ALL: wirelen solved = 543, spread = 1751, legal = 1864; time = 0.02s +Info: at iteration #4, type ALL: wirelen solved = 609, spread = 1800, legal = 1874; time = 0.01s +Info: at iteration #5, type ALL: wirelen solved = 778, spread = 1673, legal = 1775; time = 0.01s +Info: at iteration #6, type ALL: wirelen solved = 811, spread = 1700, legal = 1801; time = 0.01s +Info: at iteration #7, type ALL: wirelen solved = 904, spread = 1637, legal = 1786; time = 0.02s +Info: at iteration #8, type ALL: wirelen solved = 895, spread = 1601, legal = 1734; time = 0.01s +Info: at iteration #9, type ALL: wirelen solved = 958, spread = 1746, legal = 1829; time = 0.01s +Info: at iteration #10, type ALL: wirelen solved = 1014, spread = 1712, legal = 1802; time = 0.01s +Info: at iteration #11, type ALL: wirelen solved = 1025, spread = 1558, legal = 1719; time = 0.01s +Info: at iteration #12, type ALL: wirelen solved = 976, spread = 1526, legal = 1631; time = 0.01s +Info: at iteration #13, type ALL: wirelen solved = 946, spread = 1600, legal = 1730; time = 0.01s +Info: at iteration #14, type ALL: wirelen solved = 1017, spread = 1556, legal = 1618; time = 0.01s +Info: at iteration #15, type ALL: wirelen solved = 1103, spread = 1700, legal = 1813; time = 0.01s +Info: at iteration #16, type ALL: wirelen solved = 1257, spread = 1631, legal = 1769; time = 0.01s +Info: at iteration #17, type ALL: wirelen solved = 1227, spread = 1506, legal = 1581; time = 0.01s +Info: at iteration #18, type ALL: wirelen solved = 1158, spread = 1649, legal = 1770; time = 0.01s +Info: at iteration #19, type ALL: wirelen solved = 1211, spread = 1632, legal = 1728; time = 0.01s +Info: at iteration #20, type ALL: wirelen solved = 1214, spread = 1883, legal = 1938; time = 0.02s +Info: at iteration #21, type ALL: wirelen solved = 1357, spread = 1844, legal = 1939; time = 0.01s +Info: at iteration #22, type ALL: wirelen solved = 1367, spread = 1717, legal = 1856; time = 0.01s +Info: HeAP Placer Time: 0.49s +Info: of which solving equations: 0.23s +Info: of which spreading cells: 0.08s +Info: of which strict legalisation: 0.03s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 144, wirelen = 1581 +Info: at iteration #5: temp = 0.000000, timing cost = 243, wirelen = 1450 +Info: at iteration #10: temp = 0.000000, timing cost = 240, wirelen = 1411 +Info: at iteration #10: temp = 0.000000, timing cost = 238, wirelen = 1415 +Info: SA placement time 0.31s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.47 MHz (PASS at 25.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.60 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.05 ns + +Info: Slack histogram: +Info: legend: * represents 2 endpoint(s) +Info: + represents [1,2) endpoint(s) +Info: [ 33807, 34079) |****** +Info: [ 34079, 34351) |***********************+ +Info: [ 34351, 34623) |********************************+ +Info: [ 34623, 34895) |****************************** +Info: [ 34895, 35167) |********************************************+ +Info: [ 35167, 35439) |*****************************************+ +Info: [ 35439, 35711) |************************************************************ +Info: [ 35711, 35983) |********************************************************+ +Info: [ 35983, 36255) |*******************************************+ +Info: [ 36255, 36527) |***************************************+ +Info: [ 36527, 36799) |*************************************************+ +Info: [ 36799, 37071) |*************************+ +Info: [ 37071, 37343) |*************************+ +Info: [ 37343, 37615) |********+ +Info: [ 37615, 37887) |*****+ +Info: [ 37887, 38159) |*+ +Info: [ 38159, 38431) |*+ +Info: [ 38431, 38703) |******+ +Info: [ 38703, 38975) |****+ +Info: [ 38975, 39247) |****+ +Info: Checksum: 0xe2dca7b1 +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 2997 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 66 933 | 66 933 | 2166| 0.19 0.19| +Info: 2000 | 320 1660 | 254 727 | 1450| 0.19 0.38| +Info: 3000 | 440 2507 | 120 847 | 578| 0.13 0.51| +Info: 3692 | 550 3069 | 110 562 | 0| 0.11 0.62| +Info: Routing complete. +Info: Router1 time 0.62s +Info: Checksum: 0x9a1511d2 + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source g_uart.u_bridge.urx.bit_cnt_TRELLIS_FF_Q_3.Q +Info: routing 1.13 1.66 Net g_uart.u_bridge.urx.bit_cnt[0] (3,40) -> (2,39) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.A +Info: Defined in: +Info: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.45 2.10 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 2.10 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (2,39) -> (2,39) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 2.10 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 2.10 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN (2,39) -> (2,39) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: uart_rx.sv:64.31-64.40 +Info: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /workspaces/yosys-clean/build/share/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.44 2.55 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1$CCU2_COMB0.F +Info: routing 1.12 3.67 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0 (2,39) -> (2,38) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0$CCU2_COMB0.B +Info: logic 0.45 4.12 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0$CCU2_COMB0.FCO +Info: routing 0.00 4.12 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0$CCU2_FCI_INT (2,38) -> (2,38) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0$CCU2_COMB1.FCI +Info: logic 0.40 4.52 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0$CCU2_COMB1.F +Info: routing 0.73 5.24 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_CIN_CCU2C_COUT_S1_LUT4_D_Z_LUT4_Z_2_D[2] (2,38) -> (3,39) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.D +Info: Defined in: +Info: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 5.48 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z.F +Info: routing 0.63 6.11 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z_LUT4_Z_1_D[3] (3,39) -> (3,39) +Info: Sink g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z_LUT4_Z_1.D +Info: Defined in: +Info: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 6.35 Source g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z_LUT4_Z_1.F +Info: routing 0.13 6.48 Net g_uart.u_bridge.urx.rx_valid_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_D_3_Z_CCU2C_S1_S0_CCU2C_B0_COUT_CCU2C_CIN_S0_LUT4_D_Z[4] (3,39) -> (3,39) +Info: Sink g_uart.u_bridge.urx.shift_TRELLIS_FF_Q_4.DI +Info: setup 0.00 6.48 Source g_uart.u_bridge.urx.shift_TRELLIS_FF_Q_4.DI +Info: 2.74 ns logic, 3.74 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source uart_rx$tr_io.O +Info: routing 2.25 2.25 Net uart_rx$TRELLIS_IO_IN (0,89) -> (2,59) +Info: Sink g_uart.u_bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: Defined in: +Info: ulx3s_top.sv:13.17-13.24 +Info: setup 0.00 2.25 Source g_uart.u_bridge.urx.rx_m_TRELLIS_FF_Q.M +Info: 0.00 ns logic, 2.25 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source g_uart.hb_TRELLIS_FF_Q_1.Q +Info: routing 0.72 1.25 Net g_uart.hb[23] (5,26) -> (3,27) +Info: Sink led_LUT4_Z.D +Info: Defined in: +Info: ulx3s_top.sv:32.24-32.26 +Info: logic 0.24 1.48 Source led_LUT4_Z.F +Info: routing 1.70 3.19 Net led$TRELLIS_IO_OUT (3,27) -> (0,35) +Info: Sink led$tr_io.I +Info: Defined in: +Info: ulx3s_top.sv:12.17-12.20 +Info: 0.76 ns logic, 2.43 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 154.37 MHz (PASS at 25.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.25 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.19 ns + +Info: Slack histogram: +Info: legend: * represents 3 endpoint(s) +Info: + represents [1,3) endpoint(s) +Info: [ 33522, 33799) |+ +Info: [ 33799, 34076) |***+ +Info: [ 34076, 34353) |******************************+ +Info: [ 34353, 34630) |*********+ +Info: [ 34630, 34907) |*******+ +Info: [ 34907, 35184) |********+ +Info: [ 35184, 35461) |************+ +Info: [ 35461, 35738) |*********************+ +Info: [ 35738, 36015) |****************************************+ +Info: [ 36015, 36292) |**********************************************+ +Info: [ 36292, 36569) |************************************************************ +Info: [ 36569, 36846) |**************************************+ +Info: [ 36846, 37123) |**************************+ +Info: [ 37123, 37400) |***************+ +Info: [ 37400, 37677) |********+ +Info: [ 37677, 37954) |**+ +Info: [ 37954, 38231) |*+ +Info: [ 38231, 38508) |***+ +Info: [ 38508, 38785) |**+ +Info: [ 38785, 39062) |****+ + +Info: Program finished normally. diff --git a/results/ulx3s-smoke-uart-20260725/smoke.config b/results/ulx3s-smoke-uart-20260725/smoke.config new file mode 100644 index 0000000..9034a0b --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/smoke.config @@ -0,0 +1,1088 @@ +.device LFE5U-85F + +.comment Part: LFE5U-85F-6CABGA381 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R34C3:CIB_DSP +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R37C1:CIB_LR +arc: JA0 E1_H02W0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R46C2:ECLK_L +arc: S2W2_JINCK S2W2_JPADDI + +.tile CIB_R5C125:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C123:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R94C46:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C47:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C48:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C49:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C50:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C51:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C52:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C53:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C54:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C55:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C56:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C57:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R94C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C71:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C72:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C73:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C74:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C75:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C76:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C77:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C78:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C79:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R94C80:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C81:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R94C82:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R22C12:EBR_SPINE_UL2 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R22C67:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_HPFE0100 + +.tile MIB_R22C68:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_HPFE0100 + +.tile MIB_R36C0:PICL1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R37C0:PICL2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R46C3:LMID_0 +arc: G_LDCC1CLKI G_JPCLKT61 + +.tile MIB_R47C0:PICL0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R48C0:PICL1 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R70C67:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_HPFE0100 + +.tile MIB_R70C68:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_HPFE0100 + +.tile MIB_R95C101:PICB0 +unknown: F0B1 + +.tile MIB_R95C102:PICB1 +unknown: F0B1 + +.tile MIB_R95C103:PICB0 +unknown: F0B1 + +.tile MIB_R95C104:PICB1 +unknown: F0B1 + +.tile MIB_R95C105:PICB0 +unknown: F0B1 + +.tile MIB_R95C106:PICB1 +unknown: F0B1 + +.tile MIB_R95C107:PICB0 +unknown: F0B1 + +.tile MIB_R95C108:PICB1 +unknown: F0B1 + +.tile MIB_R95C110:PICB0 +unknown: F0B1 + +.tile MIB_R95C111:PICB1 +unknown: F0B1 + +.tile MIB_R95C112:PICB0 +unknown: F0B1 + +.tile MIB_R95C113:PICB1 +unknown: F0B1 + +.tile MIB_R95C114:PICB0 +unknown: F0B1 + +.tile MIB_R95C115:PICB1 +unknown: F0B1 + +.tile MIB_R95C116:PICB0 +unknown: F0B1 + +.tile MIB_R95C117:PICB1 +unknown: F0B1 + +.tile MIB_R95C119:PICB0 +unknown: F0B1 + +.tile MIB_R95C120:PICB1 +unknown: F0B1 + +.tile MIB_R95C121:PICB0 +unknown: F0B1 + +.tile MIB_R95C122:PICB1 +unknown: F0B1 + +.tile MIB_R95C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R95C96:PICB0 +unknown: F0B1 + +.tile MIB_R95C97:PICB1 +unknown: F0B1 + +.tile MIB_R95C98:PICB0 +unknown: F0B1 + +.tile MIB_R95C99:PICB1 +unknown: F0B1 + +.tile R30C2:PLC2 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 F2 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C2:PLC2 +arc: H00L0000 V02S0201 +arc: V00B0000 V02S0001 +arc: A0 H00L0000 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q6 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C3:PLC2 +arc: S1_V02S0201 E1_H02W0201 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C4:PLC2 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R31C5:PLC2 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H00L0000 Q2 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +arc: W1_H02W0201 Q2 +word: SLICEC.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: 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00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 0000000000FFC9030000000000000000000000000000000000020000000020000000020000000020 + 00000002000000002000000002000000002000000001800000000800000000800000000800000040 + 80000000080000000080000000080000000020000000020000000020000000020000000020000000); + +SIR 8 TDI (FF); +RUNTEST IDLE 100 TCK 1.00E-02 SEC; + +SIR 8 TDI (C0); +RUNTEST IDLE 2 TCK 1.00E-03 SEC; +SDR 32 TDI (00000000) + TDO (00000000) + MASK (FFFFFFFF); + +SIR 8 TDI (26); +RUNTEST IDLE 2 TCK 2.00E-01 SEC; + +SIR 8 TDI (FF); +RUNTEST IDLE 2 TCK 1.00E-03 SEC; + +SIR 8 TDI (3C); +SDR 32 TDI (00000000) + TDO (00000100) + MASK (00002100); diff --git a/results/ulx3s-smoke-uart-20260725/timing.txt b/results/ulx3s-smoke-uart-20260725/timing.txt new file mode 100644 index 0000000..8d1bb6c --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/timing.txt @@ -0,0 +1,4 @@ +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 352.61 MHz (PASS at 25.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 291.97 MHz (PASS at 25.00 MHz) +Info: Slack histogram: diff --git a/results/ulx3s-smoke-uart-20260725/timing_uart.txt b/results/ulx3s-smoke-uart-20260725/timing_uart.txt new file mode 100644 index 0000000..30c0e3a --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/timing_uart.txt @@ -0,0 +1,4 @@ +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.47 MHz (PASS at 25.00 MHz) +Info: Slack histogram: +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 154.37 MHz (PASS at 25.00 MHz) +Info: Slack histogram: diff --git a/results/ulx3s-smoke-uart-20260725/tool_versions.txt b/results/ulx3s-smoke-uart-20260725/tool_versions.txt new file mode 100644 index 0000000..f7fbcc9 --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/tool_versions.txt @@ -0,0 +1,5 @@ +=== TOOL VERSIONS === +Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.10-100-gfb95bb8e) +Project Trellis ecppack Version 1.4-79-g56bb170 +date: 2026-07-26T14:25:07Z diff --git a/results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt b/results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt new file mode 100644 index 0000000..e91c95b --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/tool_versions_uart.txt @@ -0,0 +1,5 @@ +=== TOOL VERSIONS (UART) === +Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) +"nextpnr-ecp5" -- Next Generation Place and Route (Version nextpnr-0.10-100-gfb95bb8e) +Project Trellis ecppack Version 1.4-79-g56bb170 +date: 2026-07-26T14:25:10Z diff --git a/results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit b/results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit new file mode 100644 index 0000000..2325234 Binary files /dev/null and b/results/ulx3s-smoke-uart-20260725/ulx3s_bridge.bit differ diff --git a/results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit b/results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit new file mode 100644 index 0000000..a66f3d6 Binary files /dev/null and b/results/ulx3s-smoke-uart-20260725/ulx3s_smoke.bit differ diff --git a/results/ulx3s-smoke-uart-20260725/yosys.log b/results/ulx3s-smoke-uart-20260725/yosys.log new file mode 100644 index 0000000..5a358d5 --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/yosys.log @@ -0,0 +1,1228 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) + +-- Running command `read_verilog -sv smoke_top.sv; hierarchy -check -top smoke_top; proc; check; synth_ecp5 -top smoke_top; write_json smoke_top.json' -- + +1. Executing Verilog-2005 frontend: smoke_top.sv +Parsing SystemVerilog input from `smoke_top.sv' to AST representation. +Generating RTLIL representation for module `\smoke_top'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \smoke_top + +2.2. Analyzing design hierarchy.. +Top module: \smoke_top +Removed 0 unused modules. + +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +3.4. Executing PROC_INIT pass (extract init attributes). + +3.5. Executing PROC_ARST pass (detect async resets in processes). + +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\smoke_top.$proc$smoke_top.sv:13$1'. + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\smoke_top.\cnt' using process `\smoke_top.$proc$smoke_top.sv:13$1'. + created $dff cell `$procdff$4' with positive edge clock. + +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `smoke_top.$proc$smoke_top.sv:13$1'. +Cleaned up 0 empty switches. + +3.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +4. Executing CHECK pass (checking for obvious problems). +Checking module smoke_top... +Found and reported 0 problems. + +5. Executing SYNTH_LATTICE pass. + +5.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +5.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +5.3. Executing HIERARCHY pass (managing design hierarchy). + +5.3.1. Analyzing design hierarchy.. +Top module: \smoke_top + +5.3.2. Analyzing design hierarchy.. +Top module: \smoke_top +Removed 0 unused modules. + +5.4. Executing PROC pass (convert processes to netlists). + +5.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +5.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +5.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +5.4.4. Executing PROC_INIT pass (extract init attributes). + +5.4.5. Executing PROC_ARST pass (detect async resets in processes). + +5.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +5.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +5.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +5.4.9. Executing PROC_DFF pass (convert process syncs to FFs). + +5.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +5.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +5.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.5. Executing CHECK pass (checking for obvious problems). +Checking module smoke_top... +Found and reported 0 problems. + +5.6. Executing FLATTEN pass (flatten design). + +5.7. Executing TRIBUF pass. + +5.8. Executing DEMINOUT pass (demote inout ports to input or output). + +5.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. +Removed 0 unused cells and 2 unused wires. + + +5.11. Executing CHECK pass (checking for obvious problems). +Checking module smoke_top... +Found and reported 0 problems. + +5.12. Executing OPT pass (performing simple optimizations). + +5.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.12.9. Finished fast OPT passes. (There is nothing left to do.) + +5.13. Executing FSM pass (extract and optimize FSM). + +5.13.1. Executing FSM_DETECT pass (finding FSMs in design). + +5.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +5.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +5.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +5.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +5.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +5.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +5.14. Executing OPT pass (performing simple optimizations). + +5.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.14.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.14.9. Finished fast OPT passes. (There is nothing left to do.) + +5.15. Executing WREDUCE pass (reducing word size of cells). + +5.16. Executing PEEPOPT pass (run peephole optimizers). + +5.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.18. Executing SHARE pass (SAT-based resource sharing). + +5.19. Executing TECHMAP pass (map to technology primitives). + +5.19.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/cmp2lut.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +5.19.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.22. Executing TECHMAP pass (map to technology primitives). + +5.22.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/mul2dsp.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +5.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.23. Executing TECHMAP pass (map to technology primitives). + +5.23.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/dsp_map_18x18.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +5.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module smoke_top: + creating $macc model for $add$smoke_top.sv:14$2 ($add). + creating $alu model for $macc $add$smoke_top.sv:14$2. + creating $alu cell for $add$smoke_top.sv:14$2: $auto$alumacc.cc:512:replace_alu$231 + created 1 $alu and 0 $macc cells. + +5.25. Executing OPT pass (performing simple optimizations). + +5.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.25.9. Finished fast OPT passes. (There is nothing left to do.) + +5.26. Executing MEMORY pass. + +5.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +5.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +5.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +5.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +5.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +5.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +5.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +5.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +5.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +5.29. Executing TECHMAP pass (map to technology primitives). + +5.29.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +5.29.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/brams_map_16kd.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +5.29.3. Continuing TECHMAP pass. +No more expansions possible. + + +5.30. Executing OPT pass (performing simple optimizations). + +5.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.30.3. Executing OPT_DFF pass (perform DFF optimizations). + +5.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.30.5. Finished fast OPT passes. + +5.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +5.32. Executing OPT pass (performing simple optimizations). + +5.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 3 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.32.9. Finished fast OPT passes. (There is nothing left to do.) + +5.33. Executing TECHMAP pass (map to technology primitives). + +5.33.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +5.33.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +5.33.3. Continuing TECHMAP pass. +Using template $paramod$c6885379b74fbbf6906b35106e386e521d86cbb2\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $logic_or. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $pos. +No more expansions possible. + + +5.34. Executing OPT pass (performing simple optimizations). + +5.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + + +5.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 77 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Computing hashes of 75 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. + +Removed a total of 2 cells. + +5.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +5.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. +Removed 36 unused cells and 73 unused wires. + + +5.34.5. Finished fast OPT passes. + +5.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +5.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 39 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.38. Executing TECHMAP pass (map to technology primitives). + +5.38.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +5.38.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + + +5.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +5.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in smoke_top. + +5.42. Executing ATTRMVCP pass (move or copy attributes). + +5.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. +Removed 0 unused cells and 100 unused wires. + + +5.44. Executing CHECK pass (checking for obvious problems). +Checking module smoke_top... +Found and reported 0 problems. + +5.45. Executing TECHMAP pass (map to technology primitives). + +5.45.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/latches_map.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +5.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.46. Executing ABC9 pass. + +5.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module smoke_top. +Found 0 SCCs. + +5.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.5. Executing TECHMAP pass (map to technology primitives). + +5.46.5.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +5.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.46.6. Executing OPT pass (performing simple optimizations). + +5.46.6.1. Executing OPT_EXPR pass (perform const folding). + +5.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +5.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +5.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +5.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +5.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +5.46.6.8. Executing OPT_EXPR pass (perform const folding). + +5.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +5.46.7. Executing TECHMAP pass (map to technology primitives). + +5.46.7.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_map.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +5.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +5.46.8. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_model.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +5.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + + +5.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +5.46.12. Executing TECHMAP pass (map to technology primitives). + +5.46.12.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +5.46.12.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +5.46.13. Executing OPT pass (performing simple optimizations). + +5.46.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + + +5.46.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 59 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Computing hashes of 57 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. + +Removed a total of 2 cells. + +5.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.46.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 57 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.46.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +5.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. +Removed 0 unused cells and 55 unused wires. + + +5.46.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.46.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \smoke_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \smoke_top. +Performed a total of 0 changes. + +5.46.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\smoke_top'. +Computing hashes of 57 cells of `\smoke_top'. +Finding duplicate cells in `\smoke_top'. +Removed a total of 0 cells. + +5.46.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +5.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \smoke_top.. + +5.46.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module smoke_top. + +5.46.13.16. Finished fast OPT passes. (There is nothing left to do.) + +5.46.14. Executing AIGMAP pass (map logic to AIG). +Module smoke_top: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +5.46.15. Executing AIGMAP pass (map logic to AIG). +Module smoke_top: replaced 0 cells with 0 new cells, skipped 39 cells. + not replaced 3 cell types: + 1 $_NOT_ + 25 TRELLIS_FF + 13 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + +5.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9). + +5.46.15.3. Executing XAIGER backend. + +Extracted 0 AND gates and 68 wires from module `smoke_top' to a netlist network with 26 inputs and 26 outputs. + +5.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +5.46.15.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 26/ 26 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 13 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 26/ 26 and = 0 lev = 0 (0.00) mem = 0.00 MB ch = 0 box = 13 bb = 0 +ABC: cst = 0 cls = 0 lit = 0 unused = 65 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 0. Ch = 0. Total mem = 0.03 MB. Peak cut mem = 0.00 MB. +ABC: P: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: P: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: F: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: A: Del = 1246.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec +ABC: Total time = 0.00 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: The network is not changed by "&mfs". +ABC: + &ps -l +ABC: /input : i/o = 26/ 26 and = 0 lev = 0 (0.00) mem = 0.00 MB box = 13 bb = 0 +ABC: Mapping (K=0) : lut = 0 edge = 0 lev = 0 (0.00) levB = 13 mem = 0.00 MB +ABC: LUT = 0 : Ave = 0.00 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.01 seconds, total: 0.01 seconds + +5.46.15.6. Executing AIGER frontend. + +Removed 0 unused cells and 209 unused wires. + +5.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 2 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 13 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 2 + +Removing temp directory. + +5.46.16. Executing TECHMAP pass (map to technology primitives). + +5.46.16.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_unmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +5.46.16.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +No more expansions possible. + +Removed 0 unused cells and 215 unused wires. + +5.47. Executing TECHMAP pass (map to technology primitives). + +5.47.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +5.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +5.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in smoke_top. +Removed 0 unused cells and 4 unused wires. + +5.49. Executing AUTONAME pass. +Renamed 56 objects in module smoke_top. + + +5.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `smoke_top'. Setting top module to smoke_top. + +5.50.1. Analyzing design hierarchy.. +Top module: \smoke_top + +5.50.2. Analyzing design hierarchy.. +Top module: \smoke_top +Removed 0 unused modules. + +5.51. Printing statistics. + +=== smoke_top === + + +----------Local Count, excluding submodules. + | + 19 wires + 67 wire bits + 19 public wires + 67 public wire bits + 2 ports + 2 port bits + 40 submodules + 13 CCU2C + 2 LUT4 + 25 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + - smoke_top + + +----------Count including submodules. + | + 19 wires + 67 wire bits + 19 public wires + 67 public wire bits + 2 ports + 2 port bits + - memories + - memory bits + - processes + - cells + 40 submodules + 13 CCU2C + 2 LUT4 + 25 TRELLIS_FF + +5.52. Executing CHECK pass (checking for obvious problems). +Checking module smoke_top... +Found and reported 0 problems. + +6. Executing JSON backend. + +End of script. Logfile hash: df534b2267, time: 0.50s, user: 0.34s, system: 0.12s, MEM: 33.38 MB peak +Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) +Time spent: 52% 21x read_verilog (0 sec), 14% 1x synth_lattice (0 sec), ... diff --git a/results/ulx3s-smoke-uart-20260725/yosys_uart.log b/results/ulx3s-smoke-uart-20260725/yosys_uart.log new file mode 100644 index 0000000..42139d2 --- /dev/null +++ b/results/ulx3s-smoke-uart-20260725/yosys_uart.log @@ -0,0 +1,2398 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) + +-- Running command ` +read_verilog -sv ulx3s_top.sv uart_bridge.sv uart_rx.sv uart_tx.sv ../../asic_core/rtl/lean_silicon_lsc1.sv ../../asic_core/rtl/leanvm_b_stream_alu.sv ../../asic_core/rtl/gf128_mul_bitstream.sv ../../asic_core/rtl/gf2n_mul_bitstream.sv; +hierarchy -check -top ulx3s_top; +proc; check; +synth_ecp5 -top ulx3s_top; +write_json ulx3s_top.json +' -- + +1. Executing Verilog-2005 frontend: ulx3s_top.sv +Parsing SystemVerilog input from `ulx3s_top.sv' to AST representation. +Generating RTLIL representation for module `\ulx3s_top'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: uart_bridge.sv +Parsing SystemVerilog input from `uart_bridge.sv' to AST representation. +Generating RTLIL representation for module `\uart_bridge'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: uart_rx.sv +Parsing SystemVerilog input from `uart_rx.sv' to AST representation. +Generating RTLIL representation for module `\uart_rx'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: uart_tx.sv +Parsing SystemVerilog input from `uart_tx.sv' to AST representation. +Generating RTLIL representation for module `\uart_tx'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: ../../asic_core/rtl/lean_silicon_lsc1.sv +Parsing SystemVerilog input from `../../asic_core/rtl/lean_silicon_lsc1.sv' to AST representation. +Generating RTLIL representation for module `\lean_silicon_lsc1'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: ../../asic_core/rtl/leanvm_b_stream_alu.sv +Parsing SystemVerilog input from `../../asic_core/rtl/leanvm_b_stream_alu.sv' to AST representation. +Generating RTLIL representation for module `\leanvm_b_stream_alu'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf128_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf128_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf128_mul_bitstream'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: ../../asic_core/rtl/gf2n_mul_bitstream.sv +Parsing SystemVerilog input from `../../asic_core/rtl/gf2n_mul_bitstream.sv' to AST representation. +Generating RTLIL representation for module `\gf2n_mul_bitstream'. +Successfully finished Verilog frontend. + +9. Executing HIERARCHY pass (managing design hierarchy). + +9.1. Analyzing design hierarchy.. +Top module: \ulx3s_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1 +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: \gf2n_mul_bitstream +Used module: \uart_tx +Used module: \uart_rx +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +9.2. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 + +9.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. +Parameter \CLK_HZ = 25000000 +Parameter \BAUD = 1000000 +Generating RTLIL representation for module `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 + +9.4. Executing AST frontend in derive mode using pre-parsed AST for module `\gf2n_mul_bitstream'. +Parameter \WIDTH = 128 +Parameter \BYTE_BITS = 8 +Parameter \MODULUS_LOW = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000111 +Generating RTLIL representation for module `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream'. + +9.5. Analyzing design hierarchy.. +Top module: \ulx3s_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1 +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx + +9.6. Analyzing design hierarchy.. +Top module: \ulx3s_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1 +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx +Removing unused module `\gf2n_mul_bitstream'. +Removing unused module `\uart_tx'. +Removing unused module `\uart_rx'. +Removed 3 unused modules. + +10. Executing PROC pass (convert processes to netlists). + +10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 5 switch rules as full_case in process $proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227 in module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Marked 12 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118 in module leanvm_b_stream_alu. +Marked 3 switch rules as full_case in process $proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79 in module leanvm_b_stream_alu. +Marked 7 switch rules as full_case in process $proc$uart_rx.sv:32$191 in module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx. +Marked 4 switch rules as full_case in process $proc$uart_tx.sv:22$182 in module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:139$25 in module uart_bridge. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:121$17 in module uart_bridge. +Marked 3 switch rules as full_case in process $proc$uart_bridge.sv:103$15 in module uart_bridge. +Marked 1 switch rules as full_case in process $proc$uart_bridge.sv:86$9 in module uart_bridge. +Removed a total of 0 dead cases. + +10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 3 redundant assignments. +Promoted 24 assignments to connections. + +10.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\uart_bridge.$proc$uart_bridge.sv:23$28'. + Set init value: \por_shift = 8'00000000 + +10.5. Executing PROC_ARST pass (detect async resets in processes). + +10.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + 1/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result[127:0]$262 + 2/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry[0:0]$264 + 3/30: $5\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value[127:0]$263 + 4/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry[0:0]$260 + 5/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value[127:0]$259 + 6/30: $4\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result[127:0]$258 + 7/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.next_value[127:0]$253 [127:120] + 8/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.next_value[127:0]$253 [119:0] + 9/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.$result[127:0]$250 + 10/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.byte_value[7:0]$252 + 11/30: $3\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.value[127:0]$251 + 12/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry[0:0]$256 + 13/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value[127:0]$255 + 14/30: $3\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result[127:0]$254 + 15/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry[0:0]$249 + 16/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value[127:0]$248 + 17/30: $2\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result[127:0]$247 + 18/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.next_value[127:0]$246 + 19/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.byte_value[7:0]$245 + 20/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.value[127:0]$244 + 21/30: $2\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.$result[127:0]$243 + 22/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry[0:0]$242 + 23/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value[127:0]$241 + 24/30: $1\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result[127:0]$240 + 25/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.next_value[127:0]$239 + 26/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.byte_value[7:0]$238 + 27/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.value[127:0]$237 + 28/30: $1\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.$result[127:0]$236 + 29/30: $0\accumulator[127:0] + 30/30: $0\a_shift[127:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. + 1/5: $0\scratch_byte[7:0] [7:1] + 2/5: $0\scratch_byte[7:0] [0] + 3/5: $0\byte_index[3:0] + 4/5: $0\state[3:0] + 5/5: $0\fault[0:0] +Creating decoders for process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. + 1/13: $2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$71.$result[7:0]$88 + 2/13: $2\rx_ready[0:0] + 3/13: $2\tx_data[7:0] + 4/13: $2\tx_valid[0:0] + 5/13: $1\rx_ready[0:0] + 6/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$71.index[3:0]$83 + 7/13: $1\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$71.$result[7:0]$82 + 8/13: $1\mul_result_shift[0:0] + 9/13: $1\mul_bit_value[0:0] + 10/13: $1\mul_bit_valid[0:0] + 11/13: $1\mul_a_valid[0:0] + 12/13: $1\tx_valid[0:0] + 13/13: $1\tx_data[7:0] +Creating decoders for process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + 1/16: $5$lookahead\shift$190[7:0]$211 + 2/16: $5$bitselwrite$pos$uart_rx.sv:64$188[31:0]$210 + 3/16: $4$lookahead\shift$190[7:0]$206 + 4/16: $4$bitselwrite$pos$uart_rx.sv:64$188[31:0]$205 + 5/16: $3$lookahead\shift$190[7:0]$203 + 6/16: $3$bitselwrite$pos$uart_rx.sv:64$188[31:0]$202 + 7/16: $2$lookahead\shift$190[7:0]$199 + 8/16: $2$bitselwrite$pos$uart_rx.sv:64$188[31:0]$198 + 9/16: $0\framing_err[0:0] + 10/16: $0\rx_valid[0:0] + 11/16: $1$lookahead\shift$190[7:0]$196 + 12/16: $1$bitselwrite$pos$uart_rx.sv:64$188[31:0]$195 + 13/16: $0\receiving[0:0] + 14/16: $0\bit_cnt[3:0] + 15/16: $0\div_cnt[15:0] + 16/16: $0\rx_data[7:0] +Creating decoders for process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:22$189'. +Creating decoders for process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + 1/5: $0\shift[8:0] + 2/5: $0\bit_cnt[3:0] + 3/5: $0\div_cnt[15:0] + 4/5: $0\tx_serial[0:0] + 5/5: $0\tx_ready[0:0] +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:23$28'. +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:139$25'. + 1/2: $0\tx_data_q[7:0] + 2/2: $0\tx_full[0:0] +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:121$17'. + 1/1: $0\rx_overrun[0:0] +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:103$15'. + 1/2: $0\rx_data_q[7:0] + 2/2: $0\rx_full[0:0] +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:86$9'. + 1/1: $0\abort_q[0:0] +Creating decoders for process `\uart_bridge.$proc$uart_bridge.sv:24$4'. +Creating decoders for process `\ulx3s_top.$proc$ulx3s_top.sv:33$1'. + +10.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\leanvm_b_stream_alu.\tx_data' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\tx_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\rx_ready' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_a_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_valid' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_bit_value' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +No latch inferred for signal `\leanvm_b_stream_alu.\mul_result_shift' from process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. + +10.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\a_shift' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1130' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\accumulator' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1131' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1132' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1133' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.byte_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1134' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\shift_in_byte$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:80$223.next_value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1135' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.$result' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1136' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.value' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1137' with positive edge clock. +Creating register for signal `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.\mul_by_x$func$../../asic_core/rtl/gf2n_mul_bitstream.sv:86$224.carry' using process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. + created $dff cell `$procdff$1138' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\fault' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. + created $dff cell `$procdff$1139' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\state' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. + created $dff cell `$procdff$1140' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\byte_index' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. + created $dff cell `$procdff$1141' with positive edge clock. +Creating register for signal `\leanvm_b_stream_alu.\scratch_byte' using process `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. + created $dff cell `$procdff$1142' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\rx_data' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1143' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\rx_valid' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1144' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\framing_err' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1145' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\div_cnt' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1146' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\bit_cnt' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1147' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\shift' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1148' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\receiving' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1149' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$bitselwrite$pos$uart_rx.sv:64$188' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1150' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$lookahead\shift$190' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. + created $dff cell `$procdff$1151' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\rx_m' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:22$189'. + created $dff cell `$procdff$1152' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.\rx_s' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:22$189'. + created $dff cell `$procdff$1153' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.\tx_ready' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + created $dff cell `$procdff$1154' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.\tx_serial' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + created $dff cell `$procdff$1155' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.\div_cnt' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + created $dff cell `$procdff$1156' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.\bit_cnt' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + created $dff cell `$procdff$1157' with positive edge clock. +Creating register for signal `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.\shift' using process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. + created $dff cell `$procdff$1158' with positive edge clock. +Creating register for signal `\uart_bridge.\tx_full' using process `\uart_bridge.$proc$uart_bridge.sv:139$25'. + created $dff cell `$procdff$1159' with positive edge clock. +Creating register for signal `\uart_bridge.\tx_data_q' using process `\uart_bridge.$proc$uart_bridge.sv:139$25'. + created $dff cell `$procdff$1160' with positive edge clock. +Creating register for signal `\uart_bridge.\rx_overrun' using process `\uart_bridge.$proc$uart_bridge.sv:121$17'. + created $dff cell `$procdff$1161' with positive edge clock. +Creating register for signal `\uart_bridge.\rx_full' using process `\uart_bridge.$proc$uart_bridge.sv:103$15'. + created $dff cell `$procdff$1162' with positive edge clock. +Creating register for signal `\uart_bridge.\rx_data_q' using process `\uart_bridge.$proc$uart_bridge.sv:103$15'. + created $dff cell `$procdff$1163' with positive edge clock. +Creating register for signal `\uart_bridge.\abort_q' using process `\uart_bridge.$proc$uart_bridge.sv:86$9'. + created $dff cell `$procdff$1164' with positive edge clock. +Creating register for signal `\uart_bridge.\por_shift' using process `\uart_bridge.$proc$uart_bridge.sv:24$4'. + created $dff cell `$procdff$1165' with positive edge clock. +Creating register for signal `\ulx3s_top.\g_uart.hb' using process `\ulx3s_top.$proc$ulx3s_top.sv:33$1'. + created $dff cell `$procdff$1166' with positive edge clock. + +10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 7 empty switches in `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. +Removing empty process `$paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream.$proc$../../asic_core/rtl/gf2n_mul_bitstream.sv:72$227'. +Found and cleaned up 23 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:214$118'. +Found and cleaned up 3 empty switches in `\leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +Removing empty process `leanvm_b_stream_alu.$proc$../../asic_core/rtl/leanvm_b_stream_alu.sv:118$79'. +Found and cleaned up 8 empty switches in `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. +Removing empty process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:32$191'. +Removing empty process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx.$proc$uart_rx.sv:22$189'. +Found and cleaned up 5 empty switches in `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. +Removing empty process `$paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx.$proc$uart_tx.sv:22$182'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:23$28'. +Found and cleaned up 4 empty switches in `\uart_bridge.$proc$uart_bridge.sv:139$25'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:139$25'. +Found and cleaned up 2 empty switches in `\uart_bridge.$proc$uart_bridge.sv:121$17'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:121$17'. +Found and cleaned up 4 empty switches in `\uart_bridge.$proc$uart_bridge.sv:103$15'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:103$15'. +Found and cleaned up 1 empty switch in `\uart_bridge.$proc$uart_bridge.sv:86$9'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:86$9'. +Removing empty process `uart_bridge.$proc$uart_bridge.sv:24$4'. +Removing empty process `ulx3s_top.$proc$ulx3s_top.sv:33$1'. +Cleaned up 57 empty switches. + +10.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. + +Optimizing module gf128_mul_bitstream. +Optimizing module leanvm_b_stream_alu. + +Optimizing module lean_silicon_lsc1. + +Optimizing module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx. + +Optimizing module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx. + +Optimizing module uart_bridge. + +Optimizing module ulx3s_top. + +11. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream... +Checking module gf128_mul_bitstream... +Checking module leanvm_b_stream_alu... +Checking module lean_silicon_lsc1... +Checking module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx... +Checking module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx... +Checking module uart_bridge... +Checking module ulx3s_top... +Found and reported 0 problems. + +12. Executing SYNTH_LATTICE pass. + +12.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /workspaces/yosys-clean/build/share/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /workspaces/yosys-clean/build/share/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +12.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +12.3. Executing HIERARCHY pass (managing design hierarchy). + +12.3.1. Analyzing design hierarchy.. +Top module: \ulx3s_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1 +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx + +12.3.2. Analyzing design hierarchy.. +Top module: \ulx3s_top +Used module: \uart_bridge +Used module: \lean_silicon_lsc1 +Used module: \leanvm_b_stream_alu +Used module: \gf128_mul_bitstream +Used module: $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx +Used module: $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx +Removed 0 unused modules. + +12.4. Executing PROC pass (convert processes to netlists). + +12.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +12.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +12.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +12.4.4. Executing PROC_INIT pass (extract init attributes). + +12.4.5. Executing PROC_ARST pass (detect async resets in processes). + +12.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +12.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +12.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +12.4.9. Executing PROC_DFF pass (convert process syncs to FFs). + +12.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +12.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +12.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Optimizing module gf128_mul_bitstream. +Optimizing module leanvm_b_stream_alu. +Optimizing module lean_silicon_lsc1. +Optimizing module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx. +Optimizing module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx. +Optimizing module uart_bridge. +Optimizing module ulx3s_top. + +12.5. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream... +Checking module gf128_mul_bitstream... +Checking module leanvm_b_stream_alu... +Checking module lean_silicon_lsc1... +Checking module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx... +Checking module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx... +Checking module uart_bridge... +Checking module ulx3s_top... +Found and reported 0 problems. + +12.6. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$c8ea1368b9929af0c8d66661afb8ae1783e33452\gf2n_mul_bitstream. +Deleting now unused module gf128_mul_bitstream. +Deleting now unused module leanvm_b_stream_alu. +Deleting now unused module lean_silicon_lsc1. +Deleting now unused module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_rx. +Deleting now unused module $paramod$6d15f8570506fca37972d8b0b02db1e36be90044\uart_tx. +Deleting now unused module uart_bridge. + + +12.7. Executing TRIBUF pass. + +12.8. Executing DEMINOUT pass (demote inout ports to input or output). + +12.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 169 unused cells and 542 unused wires. + + +12.11. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_top... +Found and reported 0 problems. + +12.12. Executing OPT pass (performing simple optimizations). + +12.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 329 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 262 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 261 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 68 cells. + +12.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\g_uart.u_bridge.\utx.$procmux$1075: \g_uart.u_bridge.utx.tx_ready -> 1'1 + Replacing known input bits on port A of cell $flatten\g_uart.u_bridge.\utx.$procmux$1072: \g_uart.u_bridge.utx.tx_ready -> 1'0 + Replacing known input bits on port A of cell $flatten\g_uart.u_bridge.\utx.$procmux$1070: \g_uart.u_bridge.utx.tx_ready -> 1'0 + Replacing known input bits on port A of cell $flatten\g_uart.u_bridge.\urx.$procmux$964: \g_uart.u_bridge.urx.receiving -> 1'1 + Replacing known input bits on port A of cell $flatten\g_uart.u_bridge.\urx.$procmux$960: \g_uart.u_bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\g_uart.u_bridge.\urx.$procmux$956: \g_uart.u_bridge.urx.receiving -> 1'1 + Replacing known input bits on port B of cell $flatten\g_uart.u_bridge.\urx.$procmux$967: \g_uart.u_bridge.urx.receiving -> 1'0 + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$833. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$835. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$838. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$868. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$886. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$889. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$904. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$841. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$726. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$738. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$750. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$762. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$862. + dead port 2/2 on $mux $flatten\g_uart.u_bridge.\urx.$procmux$865. +Removed 14 multiplexer ports. + + +12.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$721: { $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$135_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$723_CMP $auto$opt_reduce.cc:137:opt_pmux$1400 } + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$769: { $auto$opt_reduce.cc:137:opt_pmux$1404 $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP $auto$opt_reduce.cc:137:opt_pmux$1402 } + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$813: { $auto$opt_reduce.cc:137:opt_pmux$1408 $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP $auto$opt_reduce.cc:137:opt_pmux$1406 } + Optimizing cells in module \ulx3s_top. +Performed a total of 3 changes. + +12.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 252 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 244 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 241 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 11 cells. + +12.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +12.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 91 unused wires. + + +12.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +12.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$621: { $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$622_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP $auto$opt_reduce.cc:137:opt_pmux$1410 $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$526_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$610_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$529_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP } + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$572: { $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP $auto$opt_reduce.cc:137:opt_pmux$1412 $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP } + Optimizing cells in module \ulx3s_top. +Performed a total of 2 changes. + +12.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 243 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +12.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.12.16. Rerunning OPT passes. (Maybe there is more to do..) + +12.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.12.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 243 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.12.20. Executing OPT_DFF pass (perform DFF optimizations). + +12.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.12.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.12.23. Finished fast OPT passes. (There is nothing left to do.) + +12.13. Executing FSM pass (extract and optimize FSM). + +12.13.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register ulx3s_top.g_uart.u_bridge.asic.datapath_seed.state. + +12.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\g_uart.u_bridge.asic.datapath_seed.state' from module `\ulx3s_top'. + found $dff cell for state register: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procdff$1140 + root of input selection tree: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \g_uart.u_bridge.por_shift [7] + found state code: 4'0000 + found ctrl input: \g_uart.u_bridge.abort_q + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$529_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$610_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$526_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y + found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$1410 + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$622_CMP + found state code: 4'1010 + found ctrl input: \g_uart.u_bridge.asic.datapath_seed.rx_fire + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$674_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$675_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$676_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$677_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$678_CMP + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$679_CMP + found state code: 4'1001 + found state code: 4'0100 + found state code: 4'0011 + found state code: 4'0101 + found state code: 4'0001 + found state code: 4'0010 + found ctrl input: \g_uart.u_bridge.asic.datapath_seed.tx_fire + found ctrl input: \g_uart.u_bridge.asic.datapath_seed.multiplier.a_last + found state code: 4'0110 + found state code: 4'0111 + found ctrl input: \g_uart.u_bridge.asic.datapath_seed.mul_tail_last + found state code: 4'1000 + found ctrl input: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$135_Y + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$622_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$610_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$604_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$579_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$529_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$526_CMP + found ctrl output: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y + ctrl inputs: { \g_uart.u_bridge.por_shift [7] \g_uart.u_bridge.abort_q \g_uart.u_bridge.asic.datapath_seed.mul_tail_last \g_uart.u_bridge.asic.datapath_seed.rx_fire \g_uart.u_bridge.asic.datapath_seed.tx_fire $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$135_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$674_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$675_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$676_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$677_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$678_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$679_CMP \g_uart.u_bridge.asic.datapath_seed.multiplier.a_last $auto$opt_reduce.cc:137:opt_pmux$1410 } + ctrl outputs: { $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$526_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$529_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$579_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$604_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$610_CMP $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$622_CMP } + transition: 4'0000 14'0------------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-0---------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'10-1--000000-- -> 4'1010 15'010100010000000 + transition: 4'0000 14'10-1-------1-- -> 4'0001 15'000010010000000 + transition: 4'0000 14'10-1------1--- -> 4'0101 15'001010010000000 + transition: 4'0000 14'10-1-----1---- -> 4'0011 15'000110010000000 + transition: 4'0000 14'10-1----1----- -> 4'0100 15'001000010000000 + transition: 4'0000 14'10-1---1------ -> 4'1001 15'010010010000000 + transition: 4'0000 14'10-1--1------- -> 4'0000 15'000000010000000 + transition: 4'0000 14'11------------ -> 4'0000 15'000000010000000 + transition: 4'1000 14'0------------- -> 4'0000 15'000000000010000 + transition: 4'1000 14'10--0--------- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--1-------0- -> 4'1000 15'010000000010000 + transition: 4'1000 14'10--1-------1- -> 4'0000 15'000000000010000 + transition: 4'1000 14'11------------ -> 4'0000 15'000000000010000 + transition: 4'0100 14'0------------- -> 4'0000 15'000000001000000 + transition: 4'0100 14'10----------0- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--0-------1- -> 4'0100 15'001000001000000 + transition: 4'0100 14'10--1-------1- -> 4'0000 15'000000001000000 + transition: 4'0100 14'11------------ -> 4'0000 15'000000001000000 + transition: 4'0010 14'0------------- -> 4'0000 15'000000000000010 + transition: 4'0010 14'10--0--------- -> 4'0010 15'000100000000010 + transition: 4'0010 14'10--1-------0- -> 4'0001 15'000010000000010 + transition: 4'0010 14'10--1-------1- -> 4'0000 15'000000000000010 + transition: 4'0010 14'11------------ -> 4'0000 15'000000000000010 + transition: 4'1010 14'0------------- -> 4'0000 15'000000000000001 + transition: 4'1010 14'10--0--------- -> 4'1010 15'010100000000001 + transition: 4'1010 14'10--1--------- -> 4'0000 15'000000000000001 + transition: 4'1010 14'11------------ -> 4'0000 15'000000000000001 + transition: 4'0110 14'0------------- -> 4'0000 15'000001000000000 + transition: 4'0110 14'10-0---------- -> 4'0110 15'001101000000000 + transition: 4'0110 14'10-1---------- -> 4'0111 15'001111000000000 + transition: 4'0110 14'11------------ -> 4'0000 15'000001000000000 + transition: 4'0001 14'0------------- -> 4'0000 15'000000100000000 + transition: 4'0001 14'10-0---------- -> 4'0001 15'000010100000000 + transition: 4'0001 14'10-1---------- -> 4'0010 15'000100100000000 + transition: 4'0001 14'11------------ -> 4'0000 15'000000100000000 + transition: 4'1001 14'0------------- -> 4'0000 15'000000000100000 + transition: 4'1001 14'10--0--------- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10--10-------- -> 4'1001 15'010010000100000 + transition: 4'1001 14'10--11-------- -> 4'0000 15'000000000100000 + transition: 4'1001 14'11------------ -> 4'0000 15'000000000100000 + transition: 4'0101 14'0------------- -> 4'0000 15'000000000001000 + transition: 4'0101 14'10-0---------- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10-1--------0- -> 4'0101 15'001010000001000 + transition: 4'0101 14'10-1--------1- -> 4'0110 15'001100000001000 + transition: 4'0101 14'11------------ -> 4'0000 15'000000000001000 + transition: 4'0011 14'0------------- -> 4'0000 15'000000000000100 + transition: 4'0011 14'10--0--------- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--1-------0- -> 4'0011 15'000110000000100 + transition: 4'0011 14'10--1-------1- -> 4'0000 15'000000000000100 + transition: 4'0011 14'11------------ -> 4'0000 15'000000000000100 + transition: 4'0111 14'0------------- -> 4'0000 15'100000000000000 + transition: 4'0111 14'100----------- -> 4'0111 15'101110000000000 + transition: 4'0111 14'101---------0- -> 4'0110 15'101100000000000 + transition: 4'0111 14'101---------1- -> 4'1000 15'110000000000000 + transition: 4'0111 14'11------------ -> 4'0000 15'100000000000000 + +12.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413' from module `\ulx3s_top'. + Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$1410. + +12.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 32 unused cells and 32 unused wires. + + +12.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413' from module `\ulx3s_top'. + Removing unused output signal $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] [0]. + Removing unused output signal $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] [1]. + Removing unused output signal $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] [2]. + Removing unused output signal $flatten\g_uart.u_bridge.\asic.\datapath_seed.$0\state[3:0] [3]. + +12.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413' from module `\ulx3s_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ----------1 + 1000 -> ---------1- + 0100 -> --------1-- + 0010 -> -------1--- + 1010 -> ------1---- + 0110 -> -----1----- + 0001 -> ----1------ + 1001 -> ---1------- + 0101 -> --1-------- + 0011 -> -1--------- + 0111 -> 1---------- + +12.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413' from module `ulx3s_top': +------------------------------------- + + Information on FSM $fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413 (\g_uart.u_bridge.asic.datapath_seed.state): + + Number of input signals: 13 + Number of output signals: 11 + Number of state bits: 11 + + Input signals: + 0: \g_uart.u_bridge.asic.datapath_seed.multiplier.a_last + 1: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$679_CMP + 2: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$678_CMP + 3: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$677_CMP + 4: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$676_CMP + 5: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$675_CMP + 6: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$674_CMP + 7: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$135_Y + 8: \g_uart.u_bridge.asic.datapath_seed.tx_fire + 9: \g_uart.u_bridge.asic.datapath_seed.rx_fire + 10: \g_uart.u_bridge.asic.datapath_seed.mul_tail_last + 11: \g_uart.u_bridge.abort_q + 12: \g_uart.u_bridge.por_shift [7] + + Output signals: + 0: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$622_CMP + 1: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$610_CMP + 2: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$604_CMP + 3: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$592_CMP + 4: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$579_CMP + 5: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$573_CMP + 6: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$554_CMP + 7: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$530_CMP + 8: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$529_CMP + 9: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$526_CMP + 10: $flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:85$73_Y + + State encoding: + 0: 11'----------1 + 1: 11'---------1- + 2: 11'--------1-- + 3: 11'-------1--- + 4: 11'------1---- + 5: 11'-----1----- + 6: 11'----1------ + 7: 11'---1------- + 8: 11'--1-------- + 9: 11'-1--------- + 10: 11'1---------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 13'10-1--1------ -> 0 11'00010000000 + 1: 0 13'10-0--------- -> 0 11'00010000000 + 2: 0 13'11----------- -> 0 11'00010000000 + 3: 0 13'0------------ -> 0 11'00010000000 + 4: 0 13'10-1----1---- -> 2 11'00010000000 + 5: 0 13'10-1--000000- -> 4 11'00010000000 + 6: 0 13'10-1-------1- -> 6 11'00010000000 + 7: 0 13'10-1---1----- -> 7 11'00010000000 + 8: 0 13'10-1------1-- -> 8 11'00010000000 + 9: 0 13'10-1-----1--- -> 9 11'00010000000 + 10: 1 13'10--1-------1 -> 0 11'00000010000 + 11: 1 13'11----------- -> 0 11'00000010000 + 12: 1 13'0------------ -> 0 11'00000010000 + 13: 1 13'10--1-------0 -> 1 11'00000010000 + 14: 1 13'10--0-------- -> 1 11'00000010000 + 15: 2 13'10--1-------1 -> 0 11'00001000000 + 16: 2 13'11----------- -> 0 11'00001000000 + 17: 2 13'0------------ -> 0 11'00001000000 + 18: 2 13'10----------0 -> 2 11'00001000000 + 19: 2 13'10--0-------1 -> 2 11'00001000000 + 20: 3 13'10--1-------1 -> 0 11'00000000010 + 21: 3 13'11----------- -> 0 11'00000000010 + 22: 3 13'0------------ -> 0 11'00000000010 + 23: 3 13'10--0-------- -> 3 11'00000000010 + 24: 3 13'10--1-------0 -> 6 11'00000000010 + 25: 4 13'10--1-------- -> 0 11'00000000001 + 26: 4 13'11----------- -> 0 11'00000000001 + 27: 4 13'0------------ -> 0 11'00000000001 + 28: 4 13'10--0-------- -> 4 11'00000000001 + 29: 5 13'11----------- -> 0 11'01000000000 + 30: 5 13'0------------ -> 0 11'01000000000 + 31: 5 13'10-0--------- -> 5 11'01000000000 + 32: 5 13'10-1--------- -> 10 11'01000000000 + 33: 6 13'11----------- -> 0 11'00100000000 + 34: 6 13'0------------ -> 0 11'00100000000 + 35: 6 13'10-1--------- -> 3 11'00100000000 + 36: 6 13'10-0--------- -> 6 11'00100000000 + 37: 7 13'10--11------- -> 0 11'00000100000 + 38: 7 13'11----------- -> 0 11'00000100000 + 39: 7 13'0------------ -> 0 11'00000100000 + 40: 7 13'10--10------- -> 7 11'00000100000 + 41: 7 13'10--0-------- -> 7 11'00000100000 + 42: 8 13'11----------- -> 0 11'00000001000 + 43: 8 13'0------------ -> 0 11'00000001000 + 44: 8 13'10-1--------1 -> 5 11'00000001000 + 45: 8 13'10-1--------0 -> 8 11'00000001000 + 46: 8 13'10-0--------- -> 8 11'00000001000 + 47: 9 13'10--1-------1 -> 0 11'00000000100 + 48: 9 13'11----------- -> 0 11'00000000100 + 49: 9 13'0------------ -> 0 11'00000000100 + 50: 9 13'10--1-------0 -> 9 11'00000000100 + 51: 9 13'10--0-------- -> 9 11'00000000100 + 52: 10 13'11----------- -> 0 11'10000000000 + 53: 10 13'0------------ -> 0 11'10000000000 + 54: 10 13'101---------1 -> 1 11'10000000000 + 55: 10 13'101---------0 -> 5 11'10000000000 + 56: 10 13'100---------- -> 10 11'10000000000 + +------------------------------------- + +12.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\g_uart.u_bridge.asic.datapath_seed.state$1413' from module `\ulx3s_top'. + +12.14. Executing OPT pass (performing simple optimizations). + +12.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 290 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 280 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 10 cells. + +12.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 280 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.14.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procdff$1131 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procmux$492_Y, Q = \g_uart.u_bridge.asic.datapath_seed.multiplier.impl.accumulator, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1575 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procmux$492_Y, Q = \g_uart.u_bridge.asic.datapath_seed.multiplier.impl.accumulator). +Adding SRST signal on $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procdff$1130 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procmux$507_Y, Q = \g_uart.u_bridge.asic.datapath_seed.multiplier.impl.a_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1587 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$procmux$507_Y, Q = \g_uart.u_bridge.asic.datapath_seed.multiplier.impl.a_shift). +Adding SRST signal on $flatten\g_uart.u_bridge.$procdff$1159 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1094_Y, Q = \g_uart.u_bridge.tx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1599 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1094_Y, Q = \g_uart.u_bridge.tx_full). +Adding SRST signal on $flatten\g_uart.u_bridge.$procdff$1160 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1086_Y, Q = \g_uart.u_bridge.tx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1607 ($sdff) from module ulx3s_top (D = \g_uart.u_bridge.uo_out, Q = \g_uart.u_bridge.tx_data_q). +Adding SRST signal on $flatten\g_uart.u_bridge.$procdff$1162 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1119_Y, Q = \g_uart.u_bridge.rx_full, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1613 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1119_Y, Q = \g_uart.u_bridge.rx_full). +Adding SRST signal on $flatten\g_uart.u_bridge.$procdff$1163 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$procmux$1111_Y, Q = \g_uart.u_bridge.rx_data_q, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1621 ($sdff) from module ulx3s_top (D = \g_uart.u_bridge.urx.rx_data, Q = \g_uart.u_bridge.rx_data_q). +Adding SRST signal on $flatten\g_uart.u_bridge.$procdff$1164 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.$logic_or$uart_bridge.sv:88$11_Y, Q = \g_uart.u_bridge.abort_q, rval = 1'0). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1149 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$969_Y, Q = \g_uart.u_bridge.urx.receiving, rval = 1'0). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1148 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$2$lookahead\shift$190[7:0]$199, Q = \g_uart.u_bridge.urx.shift, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1629 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$or$uart_rx.sv:64$219_Y, Q = \g_uart.u_bridge.urx.shift). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1147 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$989_Y, Q = \g_uart.u_bridge.urx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$1635 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$989_Y, Q = \g_uart.u_bridge.urx.bit_cnt). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1146 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$1000_Y, Q = \g_uart.u_bridge.urx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1647 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$1000_Y, Q = \g_uart.u_bridge.urx.div_cnt). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1145 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$914_Y, Q = \g_uart.u_bridge.urx.framing_err, rval = 1'0). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1144 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$932_Y, Q = \g_uart.u_bridge.urx.rx_valid, rval = 1'0). +Adding SRST signal on $flatten\g_uart.u_bridge.\urx.$procdff$1143 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\urx.$procmux$1018_Y, Q = \g_uart.u_bridge.urx.rx_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1669 ($sdff) from module ulx3s_top (D = \g_uart.u_bridge.urx.shift, Q = \g_uart.u_bridge.urx.rx_data). +Adding SRST signal on $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procdff$1141 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$572_Y, Q = \g_uart.u_bridge.asic.datapath_seed.byte_index, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$1677 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$572_Y, Q = \g_uart.u_bridge.asic.datapath_seed.byte_index). +Adding SRST signal on $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procdff$1142 ($dff) from module ulx3s_top (D = { $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$522_Y $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$544_Y }, Q = \g_uart.u_bridge.asic.datapath_seed.scratch_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1703 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$544_Y, Q = \g_uart.u_bridge.asic.datapath_seed.scratch_byte [0]). +Adding EN signal on $auto$ff.cc:337:slice$1703 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$522_Y, Q = \g_uart.u_bridge.asic.datapath_seed.scratch_byte [7:1]). +Adding SRST signal on $flatten\g_uart.u_bridge.\utx.$procdff$1154 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1077_Y, Q = \g_uart.u_bridge.utx.tx_ready, rval = 1'1). +Adding SRST signal on $flatten\g_uart.u_bridge.\utx.$procdff$1155 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1060_Y, Q = \g_uart.u_bridge.utx.tx_serial, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$1735 ($sdff) from module ulx3s_top (D = \g_uart.u_bridge.utx.shift [0], Q = \g_uart.u_bridge.utx.tx_serial). +Adding SRST signal on $flatten\g_uart.u_bridge.\utx.$procdff$1156 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1054_Y, Q = \g_uart.u_bridge.utx.div_cnt, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1741 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1054_Y, Q = \g_uart.u_bridge.utx.div_cnt). +Adding SRST signal on $flatten\g_uart.u_bridge.\utx.$procdff$1157 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1043_Y, Q = \g_uart.u_bridge.utx.bit_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$1745 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1043_Y, Q = \g_uart.u_bridge.utx.bit_cnt). +Adding SRST signal on $flatten\g_uart.u_bridge.\utx.$procdff$1158 ($dff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1029_Y, Q = \g_uart.u_bridge.utx.shift, rval = 9'111111111). +Adding EN signal on $auto$ff.cc:337:slice$1753 ($sdff) from module ulx3s_top (D = $flatten\g_uart.u_bridge.\utx.$procmux$1029_Y, Q = \g_uart.u_bridge.utx.shift). + +12.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 52 unused cells and 75 unused wires. + + +12.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +12.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 303 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 281 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 274 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 29 cells. + +12.14.13. Executing OPT_DFF pass (perform DFF optimizations). + +12.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 29 unused wires. + + +12.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.14.16. Rerunning OPT passes. (Maybe there is more to do..) + +12.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.14.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 274 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.14.20. Executing OPT_DFF pass (perform DFF optimizations). + +12.14.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.14.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.14.23. Finished fast OPT passes. (There is nothing left to do.) + +12.15. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 2) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1750 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1688 ($ne). +Removed top 2 bits (of 3) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1644 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1642 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1638 ($ne). +Removed top 1 bits (of 2) from port B of cell ulx3s_top.$auto$opt_dff.cc:320:make_patterns_logic$1594 ($ne). +Removed top 120 bits (of 128) from mux cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$265 ($mux). +Removed top 7 bits (of 8) from mux cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$748 ($mux). +Removed top 3 bits (of 4) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$724_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$723_CMP0 ($eq). +Removed top 4 bits (of 8) from mux cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$721 ($pmux). +Removed top 7 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$679_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$678_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$677_CMP0 ($eq). +Removed top 5 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$676_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$675_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$674_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:333$135 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\utx.$eq$uart_tx.sv:40$184 ($eq). +Removed top 11 bits (of 16) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$eq$uart_rx.sv:54$201 ($eq). +Removed top 28 bits (of 32) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$le$uart_rx.sv:63$209 ($le). +Removed top 31 bits (of 32) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$sub$uart_rx.sv:64$212 ($sub). +Removed top 27 bits (of 32) from port Y of cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$sub$uart_rx.sv:64$212 ($sub). +Converting cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$neg$uart_rx.sv:64$213 ($neg) from signed to unsigned. +Removed top 1 bits (of 33) from port A of cell ulx3s_top.$flatten\g_uart.u_bridge.\urx.$neg$uart_rx.sv:64$213 ($neg). +Removed top 6 bits (of 7) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$eq$../../asic_core/rtl/leanvm_b_stream_alu.sv:83$72 ($eq). +Removed top 1 bits (of 8) from port B of cell ulx3s_top.$flatten\g_uart.u_bridge.$eq$uart_bridge.sv:84$7 ($eq). +Removed top 4 bits (of 8) from wire ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$2\status_byte$func$../../asic_core/rtl/leanvm_b_stream_alu.sv:186$71.$result[7:0]$88. +Removed top 7 bits (of 8) from wire ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.$2\tx_data[7:0]. +Removed top 120 bits (of 128) from wire ulx3s_top.$flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$265_Y. + +12.16. Executing PEEPOPT pass (run peephole optimizers). + +12.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 3 unused wires. + + +12.18. Executing SHARE pass (SAT-based resource sharing). + +12.19. Executing TECHMAP pass (map to technology primitives). + +12.19.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/cmp2lut.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +12.19.2. Continuing TECHMAP pass. +Using template $paramod$8de9ae31f210b773e84137e37ebdc8a9cec5484d\_90_lut_cmp_ for cells of type $le. +No more expansions possible. + + +12.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 3 unused wires. + + +12.22. Executing TECHMAP pass (map to technology primitives). + +12.22.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/mul2dsp.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +12.22.2. Continuing TECHMAP pass. +No more expansions possible. + + +12.23. Executing TECHMAP pass (map to technology primitives). + +12.23.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/dsp_map_18x18.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +12.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +12.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module ulx3s_top: + creating $macc model for $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:77$222 ($add). + creating $macc model for $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:61$208 ($add). + creating $macc model for $flatten\g_uart.u_bridge.\urx.$sub$uart_rx.sv:64$212 ($sub). + creating $macc model for $flatten\g_uart.u_bridge.\urx.$neg$uart_rx.sv:64$213 ($neg). + creating $macc model for $flatten\g_uart.u_bridge.\asic.\datapath_seed.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$121 ($add). + creating $macc model for $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:58$187 ($add). + creating $macc model for $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:55$186 ($add). + creating $macc model for $add$ulx3s_top.sv:33$2 ($add). + creating $alu model for $macc $add$ulx3s_top.sv:33$2. + creating $alu model for $macc $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:55$186. + creating $alu model for $macc $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:58$187. + creating $alu model for $macc $flatten\g_uart.u_bridge.\asic.\datapath_seed.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$121. + creating $alu model for $macc $flatten\g_uart.u_bridge.\urx.$neg$uart_rx.sv:64$213. + creating $alu model for $macc $flatten\g_uart.u_bridge.\urx.$sub$uart_rx.sv:64$212. + creating $alu model for $macc $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:61$208. + creating $alu model for $macc $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:77$222. + creating $alu cell for $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:77$222: $auto$alumacc.cc:512:replace_alu$1767 + creating $alu cell for $flatten\g_uart.u_bridge.\urx.$add$uart_rx.sv:61$208: $auto$alumacc.cc:512:replace_alu$1770 + creating $alu cell for $flatten\g_uart.u_bridge.\urx.$sub$uart_rx.sv:64$212: $auto$alumacc.cc:512:replace_alu$1773 + creating $alu cell for $flatten\g_uart.u_bridge.\urx.$neg$uart_rx.sv:64$213: $auto$alumacc.cc:512:replace_alu$1776 + creating $alu cell for $flatten\g_uart.u_bridge.\asic.\datapath_seed.$add$../../asic_core/rtl/leanvm_b_stream_alu.sv:262$121: $auto$alumacc.cc:512:replace_alu$1779 + creating $alu cell for $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:58$187: $auto$alumacc.cc:512:replace_alu$1782 + creating $alu cell for $flatten\g_uart.u_bridge.\utx.$add$uart_tx.sv:55$186: $auto$alumacc.cc:512:replace_alu$1785 + creating $alu cell for $add$ulx3s_top.sv:33$2: $auto$alumacc.cc:512:replace_alu$1788 + created 8 $alu and 0 $macc cells. + +12.25. Executing OPT pass (performing simple optimizations). + +12.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 274 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 274 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.25.6. Executing OPT_DFF pass (perform DFF optimizations). + +12.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.25.9. Finished fast OPT passes. (There is nothing left to do.) + +12.26. Executing MEMORY pass. + +12.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +12.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +12.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +12.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +12.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +12.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +12.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +12.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +12.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +12.29. Executing TECHMAP pass (map to technology primitives). + +12.29.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +12.29.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/brams_map_16kd.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +12.29.3. Continuing TECHMAP pass. +No more expansions possible. + + +12.30. Executing OPT pass (performing simple optimizations). + +12.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 238 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.30.3. Executing OPT_DFF pass (perform DFF optimizations). + +12.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 37 unused wires. + + +12.30.5. Finished fast OPT passes. + +12.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +12.32. Executing OPT pass (performing simple optimizations). + +12.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 236 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. + New ctrl vector for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$572: { \g_uart.u_bridge.asic.datapath_seed.state [0] $auto$opt_reduce.cc:137:opt_pmux$1925 } + Consolidated identical input bits for $pmux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.$procmux$721: + Old ports: A=4'0000, B=12'100011110001, Y=$auto$wreduce.cc:514:run$1761 [3:0] + New ports: A=3'000, B=9'100111001, Y={ $auto$wreduce.cc:514:run$1761 [3] $auto$wreduce.cc:514:run$1761 [1:0] } + New connections: $auto$wreduce.cc:514:run$1761 [2] = $auto$wreduce.cc:514:run$1761 [1] + Consolidated identical input bits for $mux cell $flatten\g_uart.u_bridge.\asic.\datapath_seed.\multiplier.\impl.$ternary$../../asic_core/rtl/gf2n_mul_bitstream.sv:66$265: + Old ports: A=8'00000000, B=8'10000111, Y={ $auto$wreduce.cc:514:run$1763 [7:1] $auto$opt_expr.cc:206:group_cell_inputs$1923 [0] } + New ports: A=1'0, B=1'1, Y=$auto$opt_expr.cc:206:group_cell_inputs$1923 [0] + New connections: $auto$wreduce.cc:514:run$1763 [7:1] = { $auto$opt_expr.cc:206:group_cell_inputs$1923 [0] 4'0000 $auto$opt_expr.cc:206:group_cell_inputs$1923 [0] $auto$opt_expr.cc:206:group_cell_inputs$1923 [0] } + Optimizing cells in module \ulx3s_top. +Performed a total of 3 changes. + +12.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 237 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +12.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 3 unused wires. + + +12.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.32.9. Rerunning OPT passes. (Maybe there is more to do..) + +12.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.32.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 236 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.32.13. Executing OPT_DFF pass (perform DFF optimizations). + +12.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 3 unused wires. + + +12.32.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.32.16. Rerunning OPT passes. (Maybe there is more to do..) + +12.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +12.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.32.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 236 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.32.20. Executing OPT_DFF pass (perform DFF optimizations). + +12.32.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.32.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.32.23. Finished fast OPT passes. (There is nothing left to do.) + +12.33. Executing TECHMAP pass (map to technology primitives). + +12.33.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +12.33.2. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +12.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $reduce_or. +Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$dde52db7035cb02b3cc5e73865788532339e3bcb\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$99501223b6f7e5af250351eeb57edb5403a5ad0b\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $pmux. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $logic_or. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $lut. +Using template $paramod$constmap:a94192c7eb070d39814c04a77002647a63207c97$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:221ea04873a4a4a5afa536fadda6ea361faa2fc2$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx'. + +12.33.20. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:221ea04873a4a4a5afa536fadda6ea361faa2fc2$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$4752. + dead port 2/2 on $mux $procmux$4758. + dead port 2/2 on $mux $procmux$4764. + dead port 2/2 on $mux $procmux$4770. +Removed 4 multiplexer ports. + + +12.33.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:221ea04873a4a4a5afa536fadda6ea361faa2fc2$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:221ea04873a4a4a5afa536fadda6ea361faa2fc2$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +No more expansions possible. + + +12.34. Executing OPT pass (performing simple optimizations). + +12.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 2225 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2062 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2035 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2033 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2032 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2031 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2030 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2029 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2028 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2027 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2026 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2025 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2024 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2023 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2022 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2021 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2020 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2019 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2018 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2017 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2016 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2015 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2014 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2013 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2012 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2011 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2010 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2009 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 2008 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 217 cells. + +12.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +12.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 128 unused cells and 866 unused wires. + + +12.34.5. Finished fast OPT passes. + +12.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +12.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 1964 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 1880 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 84 cells. + +12.38. Executing TECHMAP pass (map to technology primitives). + +12.38.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +12.38.2. Continuing TECHMAP pass. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. +No more expansions possible. + + +12.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +12.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in ulx3s_top. + +12.42. Executing ATTRMVCP pass (move or copy attributes). + +12.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 2401 unused wires. + + +12.44. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_top... +Found and reported 0 problems. + +12.45. Executing TECHMAP pass (map to technology primitives). + +12.45.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/latches_map.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +12.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +12.46. Executing ABC9 pass. + +12.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module ulx3s_top. +Found 0 SCCs. + +12.46.4. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.5. Executing TECHMAP pass (map to technology primitives). + +12.46.5.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +12.46.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +12.46.6. Executing OPT pass (performing simple optimizations). + +12.46.6.1. Executing OPT_EXPR pass (perform const folding). + +12.46.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +12.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +12.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +12.46.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +12.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +12.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +12.46.6.8. Executing OPT_EXPR pass (perform const folding). + +12.46.6.9. Finished fast OPT passes. (There is nothing left to do.) + +12.46.7. Executing TECHMAP pass (map to technology primitives). + +12.46.7.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_map.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +12.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +12.46.8. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_model.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +12.46.9. Executing ABC9_OPS pass (helper functions for ABC9). + + +12.46.10. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +12.46.12. Executing TECHMAP pass (map to technology primitives). + +12.46.12.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/techmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +12.46.12.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +12.46.13. Executing OPT pass (performing simple optimizations). + +12.46.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + + +12.46.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 59 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Computing hashes of 57 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. + +Removed a total of 2 cells. + +12.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +12.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.46.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 57 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.46.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +12.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. +Removed 0 unused cells and 55 unused wires. + + +12.46.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.46.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +12.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \ulx3s_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +12.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \ulx3s_top. +Performed a total of 0 changes. + +12.46.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\ulx3s_top'. +Computing hashes of 57 cells of `\ulx3s_top'. +Finding duplicate cells in `\ulx3s_top'. +Removed a total of 0 cells. + +12.46.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +12.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \ulx3s_top.. + +12.46.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module ulx3s_top. + +12.46.13.16. Finished fast OPT passes. (There is nothing left to do.) + +12.46.14. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_top: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +12.46.15. Executing AIGMAP pass (map logic to AIG). +Module ulx3s_top: replaced 1181 cells with 7334 new cells, skipped 699 cells. + replaced 3 cell types: + 694 $_MUX_ + 311 $_OR_ + 176 $_XOR_ + not replaced 5 cell types: + 146 $_AND_ + 96 $_NOT_ + 7 $scopeinfo + 402 TRELLIS_FF + 48 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + +12.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9). + +12.46.15.3. Executing XAIGER backend. + +Extracted 3067 AND gates and 8489 wires from module `ulx3s_top' to a netlist network with 404 inputs and 422 outputs. + +12.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +12.46.15.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 404/ 422 and = 2196 lev = 36 (2.93) mem = 0.05 MB box = 48 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 404/ 422 and = 2741 lev = 12 (2.05) mem = 0.05 MB ch = 356 box = 48 bb = 0 +ABC: cst = 0 cls = 343 lit = 356 unused = 2590 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 2741. Ch = 343. Total mem = 0.68 MB. Peak cut mem = 0.03 MB. +ABC: P: Del = 2605.00. Ar = 2031.0. Edge = 2863. Cut = 31048. T = 0.00 sec +ABC: P: Del = 2605.00. Ar = 2046.0. Edge = 2875. Cut = 31019. T = 0.00 sec +ABC: P: Del = 2605.00. Ar = 694.0. Edge = 2006. Cut = 41222. T = 0.01 sec +ABC: F: Del = 2605.00. Ar = 612.0. Edge = 1977. Cut = 40210. T = 0.01 sec +ABC: A: Del = 2605.00. Ar = 612.0. Edge = 1931. Cut = 39578. T = 0.01 sec +ABC: A: Del = 2605.00. Ar = 611.0. Edge = 1928. Cut = 39794. T = 0.01 sec +ABC: Total time = 0.03 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 404/ 422 and = 1937 lev = 12 (2.42) mem = 0.04 MB box = 34 bb = 0 +ABC: Mapping (K=6) : lut = 577 edge = 1918 lev = 5 (1.23) levB = 12 mem = 0.02 MB +ABC: LUT = 577 : 2=64 11.1 % 3=291 50.4 % 4=194 33.6 % 5=27 4.7 % 6=1 0.2 % Ave = 3.32 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.05 sec +ABC: + time +ABC: elapse: 0.16 seconds, total: 0.16 seconds + +12.46.15.6. Executing AIGER frontend. + +Removed 2990 unused cells and 4198 unused wires. + +12.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 582 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 34 +ABC RESULTS: input signals: 23 +ABC RESULTS: output signals: 48 + +Removing temp directory. + +12.46.16. Executing TECHMAP pass (map to technology primitives). + +12.46.16.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/abc9_unmap.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +12.46.16.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +No more expansions possible. + +Removed 160 unused cells and 9280 unused wires. + +12.47. Executing TECHMAP pass (map to technology primitives). + +12.47.1. Executing Verilog-2005 frontend: /workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v +Parsing Verilog input from `/workspaces/yosys-clean/build/share/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +12.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. +Using template $paramod$14af40d00c71699100007e8256a2c6a11b26feea$lut for cells of type $lut. +Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod$155e50cd807a0506e3b587eb402ba3912f883551$lut for cells of type $lut. +Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut. +Using template $paramod$15e09ab8f7df8d225706de985558fe8eca7cc41f$lut for cells of type $lut. +Using template $paramod$bf9d12be9e757c28b1374b63e168615e76b4b315$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$f4f5fb4ce8d1ecc0c1b88e4df7b6b556b55a99c1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c$lut for cells of type $lut. +Using template $paramod$64027d2d1e06b389ce9366da7d07d8faebecbcce$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99$lut for cells of type $lut. +Using template $paramod$a238bb199d4b53d4c976c9e68dafcfe86b19f40f$lut for cells of type $lut. +Using template $paramod$21972aba492c5b553603646857b0e8e9aca32466$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018$lut for cells of type $lut. +Using template $paramod$66e741791413519a466d4f44240bc83d3a191818$lut for cells of type $lut. +Using template $paramod$38621c4d710b101de242bc8b9808c74c5e2b0fe5$lut for cells of type $lut. +Using template $paramod$2b2b3565ec13859d2b24f2fa297fa46249270140$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54$lut for cells of type $lut. +Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. +Using template $paramod$351521e8b01efeb144a39a20c4d973eb0b1643fa$lut for cells of type $lut. +Using template $paramod$d93e317e4305845c36a4846fab4f21562ddc07f3$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b$lut for cells of type $lut. +Using template $paramod$71fe64ec84cd988131a5739aee02b6b2073a0ff6$lut for cells of type $lut. +Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$7c1511221ba35584fcf18be7e00c51b6a1c87a6f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$964dd3bb74caaeb47247bf4769459daf8ef427dd$lut for cells of type $lut. +Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e$lut for cells of type $lut. +Using template $paramod$5625c0c6def530beb96c16e17997d6d42e5e6d89$lut for cells of type $lut. +Using template $paramod$754105cb45ebc31318314081e9c06ede0aae4ccd$lut for cells of type $lut. +Using template $paramod$403c6d95df5fccd9225dab184f38aed47316d5b4$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. +Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163$lut for cells of type $lut. +Using template $paramod$b16305c55e8688bbbd58bd36edbb9b6878120874$lut for cells of type $lut. +Using template $paramod$cda63929d33f71c0bd57b87fcb025f6a72d7ac23$lut for cells of type $lut. +Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut. +Using template $paramod$e76f31d8d51881375bd5cd322c52ccdc4b6e3c26$lut for cells of type $lut. +Using template $paramod$91cf3b8946a6c260321b0156c1a86ce6a2bf132f$lut for cells of type $lut. +Using template $paramod$851b6023d00a4d42162085bc4dc5b63e5c0ee69e$lut for cells of type $lut. +Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. +Using template $paramod$02d41f9614523902b4f492e8631d36659becf604$lut for cells of type $lut. +Using template $paramod$ca57666f1236a8144091e90ff71c30858835882a$lut for cells of type $lut. +Using template $paramod$2008f2139fb7fa7c754eda34795a806cfb641f3e$lut for cells of type $lut. +Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. +Using template $paramod$d8021370f0670d331038a0473505efae4dff2706$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut. +Using template $paramod$c5479cb3b02237832e868d4808b3a7f1be08f618$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. +Using template $paramod$96f8aefa188f7bcda3f513a04036972753547a5b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod$2af7fd5c408581c2b6e80048f54948ce05a232f8$lut for cells of type $lut. +Using template $paramod$0c43803af5817ed91a49f985af8970f445069029$lut for cells of type $lut. +Using template $paramod$e1621a1af3641ef0ee3e4f5fe9a1fbb652e8ac6e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$8a77a4b825e7cd0e2a0cbe1bb8ec99794d7f5906$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$2e7b4eda5c0f8346612da7e971c73bc842301f6b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. +Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45$lut for cells of type $lut. +Using template $paramod$8cd5a5f75f43fffe243164dff2e5d4f1454af19a$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$08d95cc23c2f249ee5ff7158ea0a000360998a0d$lut for cells of type $lut. +Using template $paramod$5e76a98d96bc61d9446abbaea2ece5208145db09$lut for cells of type $lut. +Using template $paramod$af08867fe0bde4918ae8f1ec2010b6efc74a2fdc$lut for cells of type $lut. +Using template $paramod$4d19cda404fc60d6ab61dd511e4f73b50816875f$lut for cells of type $lut. +Using template $paramod$a77e80a763c6836e9c116105bd24c131be91f155$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +12.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in ulx3s_top. + Optimizing lut $abc$22179$lut$aiger$o313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$22179$lut$aiger22178$907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger$o311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$22179$lut$aiger22178$770.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger$o389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger$o313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger$o313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$22179$lut$aiger22178$1058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$22179$lut$aiger22178$992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$22179$lut$aiger22178$955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$22179$lut$aiger22178$737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$22179$lut$aiger22178$741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$22179$lut$aiger$o352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$22179$lut$aiger$o422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$22179$lut$aiger$o366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$22179$lut$aiger22178$1058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$22341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) +Removed 0 unused cells and 1200 unused wires. + +12.49. Executing AUTONAME pass. +Renamed 1432 objects in module ulx3s_top. + + +12.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `ulx3s_top'. Setting top module to ulx3s_top. + +12.50.1. Analyzing design hierarchy.. +Top module: \ulx3s_top + +12.50.2. Analyzing design hierarchy.. +Top module: \ulx3s_top +Removed 0 unused modules. + +12.51. Printing statistics. + +=== ulx3s_top === + + +----------Local Count, excluding submodules. + | + 437 wires + 1775 wire bits + 437 public wires + 1775 public wire bits + 4 ports + 4 port bits + 7 cells + 7 $scopeinfo + 1079 submodules + 34 CCU2C + 1 L6MUX21 + 613 LUT4 + 29 PFUMX + 402 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 7 ulx3s_top + + +----------Count including submodules. + | + 437 wires + 1775 wire bits + 437 public wires + 1775 public wire bits + 4 ports + 4 port bits + - memories + - memory bits + - processes + 7 cells + 7 $scopeinfo + 1079 submodules + 34 CCU2C + 1 L6MUX21 + 613 LUT4 + 29 PFUMX + 402 TRELLIS_FF + +12.52. Executing CHECK pass (checking for obvious problems). +Checking module ulx3s_top... +Found and reported 0 problems. + +13. Executing JSON backend. + +End of script. Logfile hash: 13d1b9a9c8, time: 1.42s, user: 1.10s, system: 0.15s, MEM: 62.34 MB peak +Yosys 0.67+94 (git sha1 7defa5186, Release, GNU /usr/bin/c++ 13.3.0) +Time spent: 19% 28x read_verilog (0 sec), 13% 1x abc9_exe (0 sec), ... diff --git a/sim/test_atomic_publish.py b/sim/test_atomic_publish.py new file mode 100644 index 0000000..46bc286 --- /dev/null +++ b/sim/test_atomic_publish.py @@ -0,0 +1,78 @@ +import os +from pathlib import Path +import subprocess +import sys +import tempfile +import time +import unittest +from unittest import mock + +from tools import atomic_publish + +SCRIPT = Path(__file__).parents[1] / "tools" / "atomic_publish.py" + + +class AtomicPublishTests(unittest.TestCase): + def make_archives(self, root): + old = root / "archive" + staged = root / ".archive-staged" + old.mkdir() + staged.mkdir() + (old / "artifact.bit").write_bytes(b"old-bitstream") + (old / "SHA256SUMS").write_text("old-manifest\n") + (staged / "artifact.bit").write_bytes(b"new-bitstream") + (staged / "SHA256SUMS").write_text("new-manifest\n") + return old, staged + + def test_success_replaces_the_complete_directory(self): + with tempfile.TemporaryDirectory() as tmp: + old, staged = self.make_archives(Path(tmp)) + atomic_publish.publish(staged, old) + self.assertEqual((old / "artifact.bit").read_bytes(), b"new-bitstream") + self.assertEqual((old / "SHA256SUMS").read_text(), "new-manifest\n") + self.assertFalse(staged.exists()) + + def test_exchange_failure_preserves_the_complete_old_archive(self): + with tempfile.TemporaryDirectory() as tmp: + old, staged = self.make_archives(Path(tmp)) + with mock.patch.object( + atomic_publish, "_exchange", side_effect=OSError("injected failure") + ): + with self.assertRaises(OSError): + atomic_publish.publish(staged, old) + self.assertEqual((old / "artifact.bit").read_bytes(), b"old-bitstream") + self.assertEqual((old / "SHA256SUMS").read_text(), "old-manifest\n") + self.assertEqual((staged / "artifact.bit").read_bytes(), b"new-bitstream") + + def test_termination_before_exchange_preserves_old_archive(self): + with tempfile.TemporaryDirectory() as tmp: + root = Path(tmp) + old, staged = self.make_archives(root) + paused = root / "paused" + env = os.environ.copy() + env["ATOMIC_PUBLISH_TEST_PAUSE_FILE"] = str(paused) + process = subprocess.Popen( + [sys.executable, str(SCRIPT), str(staged), str(old)], env=env + ) + for _ in range(200): + if paused.exists(): + break + time.sleep(0.01) + self.assertTrue(paused.exists(), "publisher did not reach test pause") + process.terminate() + self.assertNotEqual(process.wait(timeout=5), 0) + self.assertEqual((old / "artifact.bit").read_bytes(), b"old-bitstream") + self.assertEqual((old / "SHA256SUMS").read_text(), "old-manifest\n") + + def test_shared_builds_lock_before_taking_their_snapshot(self): + root = Path(__file__).parents[1] + for name in ("build_smoke.sh", "build_uart.sh"): + script = (root / "fpga" / "ulx3s" / name).read_text() + lock = script.index('"$SUPPORT" lock "$LOCK"') + snapshot = script.index('cp -a "$OUTDIR/." "$STAGE/"') + self.assertLess(lock, snapshot, f"{name} snapshots before locking") + self.assertNotIn("flock 9", script, f"{name} requires Linux flock(1)") + + +if __name__ == "__main__": + unittest.main() diff --git a/test/Makefile b/test/Makefile index 870b4e9..72e222f 100644 --- a/test/Makefile +++ b/test/Makefile @@ -4,14 +4,23 @@ PROJECT_SOURCES = \ ../asic_core/rtl/leanvm_b_stream_alu.sv \ ../asic_core/rtl/lean_silicon_lsc1.sv -.PHONY: sim stream-sim packet-frontend-sim packet-frontend-mutation clean +BRIDGE_SOURCES = \ + ../fpga/ulx3s/uart_rx.sv \ + ../fpga/ulx3s/uart_tx.sv \ + ../fpga/ulx3s/uart_bridge.sv -sim: stream-sim packet-frontend-sim packet-frontend-mutation +.PHONY: sim stream-alu uart-bridge packet-frontend-sim packet-frontend-mutation clean -stream-sim: +sim: stream-alu uart-bridge packet-frontend-sim packet-frontend-mutation + +stream-alu: iverilog -g2012 -Wall -s tb_stream_alu -o tb_stream_alu.vvp $(PROJECT_SOURCES) tb_stream_alu.sv vvp tb_stream_alu.vvp +uart-bridge: + iverilog -g2012 -Wall -s tb_uart_bridge -o tb_uart_bridge.vvp $(PROJECT_SOURCES) $(BRIDGE_SOURCES) tb_uart_bridge.sv + vvp tb_uart_bridge.vvp + packet-frontend-sim: $(MAKE) -C packet_frontend sim @@ -19,5 +28,5 @@ packet-frontend-mutation: $(MAKE) -C packet_frontend mutation clean: - rm -f tb_stream_alu.vvp + rm -f tb_stream_alu.vvp tb_uart_bridge.vvp $(MAKE) -C packet_frontend clean diff --git a/test/tb_uart_bridge.sv b/test/tb_uart_bridge.sv new file mode 100644 index 0000000..06f757b --- /dev/null +++ b/test/tb_uart_bridge.sv @@ -0,0 +1,266 @@ +`timescale 1ns/1ps +`default_nettype none +/* + * Self-checking testbench for the UART bridge and the exact lean_silicon_lsc1 + * pin boundary. + * + * The bench contains a real 1 Mbaud 8N1 receiver rather than an activity + * counter, so three failure modes that a liveness window cannot see are fatal + * here: a response byte the bridge never serialises, a byte whose final data + * bit is not held for a full baud interval, and a response that does not match + * the independently computed expected value. + */ +module tb_uart_bridge; + + localparam integer CLK_HALF_NS = 20; // 25 MHz + localparam integer BIT_NS = 1000; // 1 Mbaud + localparam integer MAX_BYTES = 64; + + reg clk = 1'b0; + always #(CLK_HALF_NS) clk = ~clk; + + reg uart_rx = 1'b1; + wire uart_tx; + + uart_bridge dut ( + .clk(clk), + .uart_rx(uart_rx), + .uart_tx(uart_tx) + ); + + integer errors = 0; + + // ---------------------------------------------------------------- host TX + task automatic send_byte(input [7:0] b); + integer i; + begin + uart_rx = 1'b0; + #(BIT_NS); + for (i = 0; i < 8; i = i + 1) begin + uart_rx = b[i]; + #(BIT_NS); + end + uart_rx = 1'b1; + #(BIT_NS); + end + endtask + + // ------------------------------------------------- host RX (real receiver) + reg [7:0] rx_bytes [0:MAX_BYTES-1]; + integer rx_count = 0; + integer rx_frame_error = 0; + + initial begin : uart_receiver + reg [7:0] b; + integer i; + forever begin + @(negedge uart_tx); + #(BIT_NS / 2); + if (uart_tx === 1'b0) begin + for (i = 0; i < 8; i = i + 1) begin + #(BIT_NS); + b[i] = uart_tx; + end + #(BIT_NS); + if (uart_tx !== 1'b1) begin + rx_frame_error = rx_frame_error + 1; + $display("FAIL stop bit not high after byte %02h", b); + end + if (rx_count < MAX_BYTES) rx_bytes[rx_count] = b; + rx_count = rx_count + 1; + end + end + end + + // ------------------------------------------------------------- expectation + reg [7:0] exp_bytes [0:MAX_BYTES-1]; + integer exp_count = 0; + + task automatic expect_reset; + begin + rx_count = 0; + exp_count = 0; + end + endtask + + task automatic expect_byte(input [7:0] b); + begin + exp_bytes[exp_count] = b; + exp_count = exp_count + 1; + end + endtask + + // Waits for the expected number of bytes, then settles to catch extras. + task automatic check_response(input [8*24-1:0] label); + integer waited; + integer i; + integer limit; + begin + // Generous budget: every response in this bench is <= 16 bytes. + limit = 40 * (exp_count + 4); + waited = 0; + while (rx_count < exp_count && waited < limit) begin + #(BIT_NS); + waited = waited + 1; + end + + if (rx_count < exp_count) begin + $display("FAIL %0s: missing TX, expected %0d byte(s), received %0d", + label, exp_count, rx_count); + errors = errors + 1; + end else begin + // Settle so a spurious extra byte is observed rather than missed. + #(BIT_NS * 14); + if (rx_count != exp_count) begin + $display("FAIL %0s: expected %0d byte(s), received %0d", + label, exp_count, rx_count); + errors = errors + 1; + end + end + + for (i = 0; i < exp_count; i = i + 1) begin + if (i < rx_count && rx_bytes[i] !== exp_bytes[i]) begin + $display("FAIL %0s: byte %0d is %02h, expected %02h", + label, i, rx_bytes[i], exp_bytes[i]); + errors = errors + 1; + end + end + + if (dut.rx_overrun !== 1'b0) begin + $display("FAIL %0s: bridge reported a receive overrun", label); + errors = errors + 1; + end + end + endtask + + // --------------------------------------------------------------- vectors + // MUL operands and the product, computed independently by sim/model.py + // (schoolbook carry-less product plus long reduction, cross-checked against + // the LSB-first bit-serial model) over GF(2^128) / x^128 + x^7 + x^2 + x + 1. + reg [7:0] mul_a [0:15]; + reg [7:0] mul_b [0:15]; + reg [7:0] mul_exp [0:15]; + + task automatic load_mul_vector; + begin + mul_a[0]=8'h11; mul_a[1]=8'h22; mul_a[2]=8'h33; mul_a[3]=8'h44; + mul_a[4]=8'h55; mul_a[5]=8'h66; mul_a[6]=8'h77; mul_a[7]=8'h88; + mul_a[8]=8'h99; mul_a[9]=8'haa; mul_a[10]=8'hbb; mul_a[11]=8'hcc; + mul_a[12]=8'hdd; mul_a[13]=8'hee; mul_a[14]=8'hff; mul_a[15]=8'h01; + + mul_b[0]=8'h02; mul_b[1]=8'h00; mul_b[2]=8'h00; mul_b[3]=8'h00; + mul_b[4]=8'h00; mul_b[5]=8'h00; mul_b[6]=8'h00; mul_b[7]=8'h00; + mul_b[8]=8'h00; mul_b[9]=8'h00; mul_b[10]=8'h00; mul_b[11]=8'h00; + mul_b[12]=8'h00; mul_b[13]=8'h00; mul_b[14]=8'h00; mul_b[15]=8'h00; + + mul_exp[0]=8'h22; mul_exp[1]=8'h44; mul_exp[2]=8'h66; mul_exp[3]=8'h88; + mul_exp[4]=8'haa; mul_exp[5]=8'hcc; mul_exp[6]=8'hee; mul_exp[7]=8'h10; + mul_exp[8]=8'h33; mul_exp[9]=8'h55; mul_exp[10]=8'h77; mul_exp[11]=8'h99; + mul_exp[12]=8'hbb; mul_exp[13]=8'hdd; mul_exp[14]=8'hff; mul_exp[15]=8'h03; + end + endtask + + integer i; + reg [7:0] set_payload [0:15]; + reg [7:0] xor_a [0:15]; + reg [7:0] xor_b [0:15]; + + initial begin + $display("tb_uart_bridge start"); + load_mul_vector; + #(BIT_NS * 4); + + // ---- STATUS: exactly four bytes must reach the host ---------------- + expect_reset; + send_byte(8'h7e); + expect_byte(8'h01); + expect_byte(8'h01); + expect_byte(8'h0f); + expect_byte(8'h08); + check_response("STATUS"); + + // ---- SET128 with an all-zero payload ------------------------------- + // Every echoed byte has bit 7 clear, so a final data bit that is not + // held for a full baud interval is received as 80 instead of 00. + expect_reset; + send_byte(8'h03); + for (i = 0; i < 16; i = i + 1) begin + set_payload[i] = 8'h00; + send_byte(set_payload[i]); + end + for (i = 0; i < 16; i = i + 1) expect_byte(set_payload[i]); + check_response("SET zero"); + + // ---- SET128 with a mixed payload ----------------------------------- + expect_reset; + send_byte(8'h03); + for (i = 0; i < 16; i = i + 1) begin + set_payload[i] = i[7:0] ^ 8'h5a; + send_byte(set_payload[i]); + end + for (i = 0; i < 16; i = i + 1) expect_byte(set_payload[i]); + check_response("SET mixed"); + + // ---- XOR128 --------------------------------------------------------- + expect_reset; + send_byte(8'h01); + for (i = 0; i < 16; i = i + 1) begin + xor_a[i] = 8'ha5 + i[7:0]; + xor_b[i] = 8'h3c ^ i[7:0]; + send_byte(xor_a[i]); + send_byte(xor_b[i]); + end + for (i = 0; i < 16; i = i + 1) expect_byte(xor_a[i] ^ xor_b[i]); + check_response("XOR"); + + // ---- MUL128 against the independent oracle vector ------------------- + expect_reset; + send_byte(8'h02); + for (i = 0; i < 16; i = i + 1) send_byte(mul_a[i]); + for (i = 0; i < 16; i = i + 1) send_byte(mul_b[i]); + for (i = 0; i < 16; i = i + 1) expect_byte(mul_exp[i]); + check_response("MUL"); + + // ---- Unknown opcode must report a protocol fault, not silence ------- + expect_reset; + send_byte(8'hff); + expect_byte(8'he0); + check_response("BAD OPCODE"); + + // ---- Abort recovery: 0x7f mid-command, then STATUS still answers ---- + expect_reset; + send_byte(8'h03); + send_byte(8'h7f); + #(BIT_NS * 20); + expect_reset; + send_byte(8'h7e); + expect_byte(8'h01); + expect_byte(8'h01); + expect_byte(8'h0f); + expect_byte(8'h08); + check_response("STATUS after abort"); + + if (rx_frame_error != 0) begin + $display("FAIL %0d framing error(s) on the bridge transmit line", + rx_frame_error); + errors = errors + 1; + end + + if (errors != 0) begin + $display("tb_uart_bridge FAILED with %0d error(s)", errors); + $fatal(1, "tb_uart_bridge failed"); + end + + $display("tb_uart_bridge PASSED"); + $finish; + end + + // Hard stop so a bridge that never transmits cannot hang the suite. + initial begin + #20_000_000; + $display("FAIL tb_uart_bridge global timeout"); + $fatal(1, "tb_uart_bridge timeout"); + end + +endmodule +`default_nettype wire diff --git a/tools/atomic_publish.py b/tools/atomic_publish.py new file mode 100644 index 0000000..613921b --- /dev/null +++ b/tools/atomic_publish.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python3 +"""Atomically replace a result directory with a verified staged directory.""" + +from __future__ import annotations + +import argparse +import ctypes +import errno +import os +from pathlib import Path +import shutil +import signal + +AT_FDCWD_LINUX = -100 +AT_FDCWD_DARWIN = -2 +RENAME_EXCHANGE = 2 +# Darwin calls the equivalent operation RENAME_SWAP. It deliberately has the +# same value as Linux's RENAME_EXCHANGE, but keeping a separately named +# constant makes the two ABIs and their intent explicit. +RENAME_SWAP = 2 + + +def _exchange(left: Path, right: Path) -> None: + """Atomically swap two same-parent directories. + + Linux provides renameat2(RENAME_EXCHANGE); macOS provides the equivalent + renameatx_np(RENAME_SWAP). A copy/delete fallback is intentionally not + used: it could expose a mixed archive or lose the old archive if the + publisher is interrupted between operations. + """ + libc = ctypes.CDLL(None, use_errno=True) + renameat2 = getattr(libc, "renameat2", None) + if renameat2 is not None: + result = renameat2( + AT_FDCWD_LINUX, + os.fsencode(left), + AT_FDCWD_LINUX, + os.fsencode(right), + RENAME_EXCHANGE, + ) + if not result: + return + error = ctypes.get_errno() + raise OSError(error, os.strerror(error)) + + # renameatx_np is the documented Darwin operation for atomically swapping + # two directory entries. It is available on the macOS host workflow even + # though that platform has no Linux renameat2 symbol. + renameatx_np = getattr(libc, "renameatx_np", None) + if renameatx_np is not None: + result = renameatx_np( + AT_FDCWD_DARWIN, + os.fsencode(left), + AT_FDCWD_DARWIN, + os.fsencode(right), + RENAME_SWAP, + ) + if not result: + return + error = ctypes.get_errno() + raise OSError(error, os.strerror(error)) + + raise OSError( + errno.ENOSYS, + "atomic directory exchange requires renameat2 (Linux) or " + "renameatx_np (macOS)", + ) + + +def publish(staged: Path, destination: Path) -> None: + staged = staged.resolve() + destination = destination.resolve() + if not staged.is_dir() or not destination.is_dir(): + raise ValueError("staged and destination must both be directories") + if staged.parent != destination.parent: + raise ValueError("staged and destination must share a parent filesystem") + _exchange(staged, destination) + shutil.rmtree(staged) + + +def main() -> int: + parser = argparse.ArgumentParser() + parser.add_argument("staged", type=Path) + parser.add_argument("destination", type=Path) + args = parser.parse_args() + pause_file = os.environ.get("ATOMIC_PUBLISH_TEST_PAUSE_FILE") + if pause_file: + Path(pause_file).touch() + signal.pause() + publish(args.staged, args.destination) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/portable_build_support.py b/tools/portable_build_support.py new file mode 100644 index 0000000..af7cc60 --- /dev/null +++ b/tools/portable_build_support.py @@ -0,0 +1,126 @@ +#!/usr/bin/env python3 +"""Portable locking and SHA-256 manifests for ULX3S build archives. + +``fcntl.flock`` is an advisory kernel lock available on both Linux and macOS. +Keeping it in this small wrapper lets the POSIX shell build scripts hold the +lock for their complete lifetime without depending on a platform-specific +``flock`` command. Hashing is likewise kept in Python's standard library so +stock macOS need not provide GNU coreutils' ``sha256sum``. +""" + +from __future__ import annotations + +import argparse +import fcntl +import hashlib +import os +from pathlib import Path +import signal +import subprocess +import sys + + +def digest(path: Path) -> str: + hasher = hashlib.sha256() + with path.open("rb") as source: + for block in iter(lambda: source.read(1024 * 1024), b""): + hasher.update(block) + return hasher.hexdigest() + + +def write_manifest(directory: Path, names: list[str], output: str) -> None: + lines = [] + for name in names: + path = directory / name + if Path(name).name != name or not path.is_file(): + raise ValueError(f"manifest input must be a file directly in archive: {name}") + lines.append(f"{digest(path)} {name}\n") + (directory / output).write_text("".join(lines), encoding="ascii") + + +def check_manifest(directory: Path, manifest: str) -> None: + failed = False + entries = 0 + for line in (directory / manifest).read_text(encoding="ascii").splitlines(): + try: + expected, name = line.split(" ", 1) + if len(expected) != 64 or any(char not in "0123456789abcdef" for char in expected): + raise ValueError + if Path(name).name != name or not name: + raise ValueError + entries += 1 + actual = digest(directory / name) + except (OSError, ValueError): + print(f"{line}: FAILED", file=sys.stderr) + failed = True + continue + if actual == expected: + print(f"{name}: OK") + else: + print(f"{name}: FAILED", file=sys.stderr) + failed = True + if entries == 0: + print(f"{manifest}: FAILED (no well-formed checksum entries)", file=sys.stderr) + failed = True + if failed: + raise SystemExit(1) + + +def locked(lock_path: Path, command: list[str]) -> int: + lock_path.parent.mkdir(parents=True, exist_ok=True) + with lock_path.open("a+") as lock: + fcntl.flock(lock, fcntl.LOCK_EX) + # Start in its own session so the shell and its toolchain children + # (yosys, nextpnr, ecppack) form a distinct process group. This lets + # forwarded cancellation reach grandchildren that the shell would + # otherwise leave running while it defers its own trap. + child = subprocess.Popen( + command, + env=os.environ | {"ULX3S_BUILD_LOCKED": "1"}, + start_new_session=True, + ) + + def forward(signum: int, _frame: object) -> None: + if child.poll() is None: + try: + os.killpg(child.pid, signum) + except ProcessLookupError: + pass + + signal.signal(signal.SIGINT, forward) + signal.signal(signal.SIGTERM, forward) + return child.wait() + + +def main() -> int: + parser = argparse.ArgumentParser() + commands = parser.add_subparsers(dest="action", required=True) + lock = commands.add_parser("lock") + lock.add_argument("lock", type=Path) + lock.add_argument("command", nargs=argparse.REMAINDER) + manifest = commands.add_parser("manifest") + manifest.add_argument("directory", type=Path) + manifest.add_argument("output") + manifest.add_argument("names", nargs="+") + check = commands.add_parser("check") + check.add_argument("directory", type=Path) + check.add_argument("manifest") + single = commands.add_parser("digest") + single.add_argument("file", type=Path) + args = parser.parse_args() + if args.action == "lock": + if not args.command: + parser.error("lock command must follow --") + return locked(args.lock, args.command) + if args.action == "manifest": + write_manifest(args.directory, args.names, args.output) + return 0 + if args.action == "digest": + print(digest(args.file)) + return 0 + check_manifest(args.directory, args.manifest) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/source_provenance.py b/tools/source_provenance.py new file mode 100644 index 0000000..50a4d38 --- /dev/null +++ b/tools/source_provenance.py @@ -0,0 +1,103 @@ +#!/usr/bin/env python3 +"""Record the source revision and per-file digests a build's inputs came from. + +An evidence archive that names a revision not containing its own build inputs +cannot be reproduced or audited: the reader cannot tell which sources produced +the bitstream. Naming the revision alone is also not enough, because a build run +from a modified worktree does not match any revision. Both are therefore +recorded, and the dirty flag is computed over the build inputs rather than the +whole tree -- a build writes its own products into results/, so a whole-tree +comparison would report "dirty" on every successful run and mean nothing. + +When the revision cannot be determined at all -- an exported tarball, or no git +on PATH -- there is nothing to compare against, so the match is reported as +"unknown" rather than "yes". Claiming the inputs agree with a revision that was +never identified is a stronger statement than the evidence supports. + +Usage: source_provenance.py ... +""" +from hashlib import sha256 +from pathlib import Path +from subprocess import DEVNULL, CalledProcessError, check_output +import sys + +ROOT = Path(__file__).resolve().parents[1] + + +def verify(manifest: Path) -> int: + """Revalidate recorded inputs immediately before artifact publication.""" + failed = False + entries = 0 + for line in manifest.read_text(encoding="ascii").splitlines(): + parts = line.split() + if len(parts) != 2 or len(parts[0]) != 64: + continue + expected, rel = parts + if any(char not in "0123456789abcdef" for char in expected): + continue + path = (ROOT / rel).resolve() + try: + path.relative_to(ROOT) + actual = sha256(path.read_bytes()).hexdigest() + except (OSError, ValueError): + actual = "" + entries += 1 + if actual != expected: + print(f"{rel}: CHANGED DURING BUILD", file=sys.stderr) + failed = True + if entries == 0: + print(f"{manifest}: no source digest entries", file=sys.stderr) + failed = True + return 1 if failed else 0 + + +def _git(*args: str) -> str: + return check_output(["git", *args], cwd=ROOT, stderr=DEVNULL).decode().strip() + + +def main(argv: list[str]) -> int: + if len(argv) == 2 and argv[0] == "--check": + return verify(Path(argv[1])) + if len(argv) < 2: + raise SystemExit( + "usage: source_provenance.py ... | " + "source_provenance.py --check " + ) + out, sources = Path(argv[0]), argv[1:] + + try: + revision = _git("rev-parse", "HEAD") + except (CalledProcessError, FileNotFoundError): + revision = "unknown" + + lines = ["=== SOURCE PROVENANCE ==="] + digests = [] + dirty = False + for src in sorted(sources): + # Resolved against the caller's directory: the build scripts run from + # fpga/ulx3s and name their inputs relative to it. + path = Path(src).resolve() + rel = path.relative_to(ROOT).as_posix() + digest = sha256(path.read_bytes()).hexdigest() + digests.append(f"{digest} {rel}") + if revision != "unknown": + try: + committed = _git("rev-parse", f"HEAD:{rel}") + dirty |= committed != _git("hash-object", str(path)) + except CalledProcessError: + dirty = True # not present at HEAD at all + + lines.append(f"revision: {revision}") + if revision == "unknown": + matched = "unknown" # nothing was compared, so "yes" would be unearned + else: + matched = "no" if dirty else "yes" + lines.append(f"inputs-match-revision: {matched}") + lines.extend(digests) + out.write_text("\n".join(lines) + "\n") + print("\n".join(lines)) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main(sys.argv[1:]))