Hello, your work has been very inspiring to me. But I encountered some problems while running the repository code. Firstly, the testbench you provided was unable to simulate properly. I am not familiar with the SystemVerilog language, so I wrote a simple testbench myself. The simulation waveform appeared to be problematic, and the written data was not read correctly. Looking forward to your reply!
Hello, your work has been very inspiring to me. But I encountered some problems while running the repository code. Firstly, the testbench you provided was unable to simulate properly. I am not familiar with the SystemVerilog language, so I wrote a simple testbench myself. The simulation waveform appeared to be problematic, and the written data was not read correctly. Looking forward to your reply!